From: Dmitry Osipenko Date: Tue, 30 Nov 2021 23:23:45 +0000 (+0300) Subject: ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=1caf3ef4c0febbfe3180da3a57e53ebfa4a0fa3b;p=linux.git ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Memory access must be blocked before hardware reset is asserted and before power is gated, otherwise a serious hardware fault is inevitable. Add reset for memory clients to the GR2D, GR3D and Host1x nodes. Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 45fe111705aff..4068952cc6c0f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -40,8 +40,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA20_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; + reset-names = "host1x", "mc"; power-domains = <&pd_core>; operating-points-v2 = <&host1x_dvfs_opp_table>; @@ -98,8 +98,8 @@ reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; + resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; + reset-names = "2d", "mc"; power-domains = <&pd_core>; operating-points-v2 = <&gr2d_dvfs_opp_table>; }; @@ -108,8 +108,8 @@ compatible = "nvidia,tegra20-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; + resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; + reset-names = "3d", "mc"; power-domains = <&pd_3d>; operating-points-v2 = <&gr3d_dvfs_opp_table>; };