From: Will Deacon <will.deacon@arm.com>
Date: Wed, 1 May 2019 14:45:36 +0000 (+0100)
Subject: Merge branch 'for-next/timers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64... 
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=24cf262da1ad303fc940c798aab0bd1bd50e3fc2;p=linux.git

Merge branch 'for-next/timers' of git://git./linux/kernel/git/arm64/linux into for-next/core

Conflicts:
	arch/arm64/Kconfig
	arch/arm64/include/asm/arch_timer.h
---

24cf262da1ad303fc940c798aab0bd1bd50e3fc2
diff --cc arch/arm64/Kconfig
index b5c6943225ce0,fcda4e21fa8fe..1c0cb5131c2ab
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@@ -477,15 -475,17 +477,17 @@@ config ARM64_ERRATUM_102471
  	  If unsure, say Y.
  
  config ARM64_ERRATUM_1188873
- 	bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
+ 	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
  	default y
+ 	depends on COMPAT
  	select ARM_ARCH_TIMER_OOL_WORKAROUND
  	help
- 	  This option adds a workaround for ARM Cortex-A76 erratum 1188873.
 -	  This option adds work arounds for ARM Cortex-A76/Neoverse-N1
 -	  erratum 1188873
++	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
++	  erratum 1188873.
  
- 	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
- 	  register corruption when accessing the timer registers from
- 	  AArch32 userspace.
+ 	  Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could
+ 	  cause register corruption when accessing the timer registers
+ 	  from AArch32 userspace.
  
  	  If unsure, say Y.
  
diff --cc arch/arm64/include/asm/arch_timer.h
index 93e07512b4b61,48b2100f4aaad..b7bca1ae09e66
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@@ -148,47 -174,30 +174,67 @@@ static inline void arch_timer_set_cntkc
  	isb();
  }
  
 +/*
 + * Ensure that reads of the counter are treated the same as memory reads
 + * for the purposes of ordering by subsequent memory barriers.
 + *
 + * This insanity brought to you by speculative system register reads,
 + * out-of-order memory accesses, sequence locks and Thomas Gleixner.
 + *
 + * http://lists.infradead.org/pipermail/linux-arm-kernel/2019-February/631195.html
 + */
 +#define arch_counter_enforce_ordering(val) do {				\
 +	u64 tmp, _val = (val);						\
 +									\
 +	asm volatile(							\
 +	"	eor	%0, %1, %1\n"					\
 +	"	add	%0, sp, %0\n"					\
 +	"	ldr	xzr, [%0]"					\
 +	: "=r" (tmp) : "r" (_val));					\
 +} while (0)
 +
- static inline u64 arch_counter_get_cntpct(void)
+ static inline u64 __arch_counter_get_cntpct_stable(void)
  {
 +	u64 cnt;
 +
  	isb();
 -	return arch_timer_reg_read_stable(cntpct_el0);
 +	cnt = arch_timer_reg_read_stable(cntpct_el0);
 +	arch_counter_enforce_ordering(cnt);
 +	return cnt;
  }
  
- static inline u64 arch_counter_get_cntvct(void)
+ static inline u64 __arch_counter_get_cntpct(void)
+ {
++	u64 cnt;
++
+ 	isb();
 -	return read_sysreg(cntpct_el0);
++	cnt = read_sysreg(cntpct_el0);
++	arch_counter_enforce_ordering(cnt);
++	return cnt;
+ }
+ 
+ static inline u64 __arch_counter_get_cntvct_stable(void)
  {
 +	u64 cnt;
 +
  	isb();
 -	return arch_timer_reg_read_stable(cntvct_el0);
 +	cnt = arch_timer_reg_read_stable(cntvct_el0);
 +	arch_counter_enforce_ordering(cnt);
 +	return cnt;
  }
  
+ static inline u64 __arch_counter_get_cntvct(void)
+ {
++	u64 cnt;
++
+ 	isb();
 -	return read_sysreg(cntvct_el0);
++	cnt = read_sysreg(cntvct_el0);
++	arch_counter_enforce_ordering(cnt);
++	return cnt;
+ }
+ 
 +#undef arch_counter_enforce_ordering
 +
  static inline int arch_timer_arch_init(void)
  {
  	return 0;
diff --cc arch/arm64/kernel/cpu_errata.c
index 1b9ce0fdd81de,06f1c8aae1dcb..e88d4e7bdfc71
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@@ -797,14 -731,13 +807,13 @@@ const struct arm64_cpu_capabilities arm
  		.capability = ARM64_SSBD,
  		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
  		.matches = has_ssbd_mitigation,
 +		.midr_range_list = arm64_ssb_cpus,
  	},
 -#endif
  #ifdef CONFIG_ARM64_ERRATUM_1188873
  	{
- 		/* Cortex-A76 r0p0 to r2p0 */
  		.desc = "ARM erratum 1188873",
  		.capability = ARM64_WORKAROUND_1188873,
- 		ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
+ 		ERRATA_MIDR_RANGE_LIST(erratum_1188873_list),
  	},
  #endif
  #ifdef CONFIG_ARM64_ERRATUM_1165522