From: Jason Gunthorpe <jgg@nvidia.com>
Date: Tue, 22 Jun 2021 18:08:39 +0000 (-0300)
Subject: Merge branch 'mlx5_realtime_ts' into rdma.git for-next
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=2833c977c3049f521784e8954d4c90e4941187db;p=linux.git

Merge branch 'mlx5_realtime_ts' into rdma.git for-next

Aharon Landau says:

====================
In case device supports only real-time timestamp, the kernel will fail to
create QP despite rdma-core requested such timestamp type.

It is because device returns free-running timestamp, and the conversion
from free-running to real-time is performed in the user space.

This series fixes it, by returning real-time timestamp.
====================

* mlx5_realtime_ts:
  RDMA/mlx5: Support real-time timestamp directly from the device
  RDMA/mlx5: Refactor get_ts_format functions to simplify code

Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
---

2833c977c3049f521784e8954d4c90e4941187db
diff --cc drivers/infiniband/hw/mlx5/main.c
index a536bdd6a9167,a273cbb9369f8..46136b4b578dc
--- a/drivers/infiniband/hw/mlx5/main.c
+++ b/drivers/infiniband/hw/mlx5/main.c
@@@ -1816,11 -1816,13 +1816,17 @@@ static int set_ucontext_resp(struct ib_
  	if (MLX5_CAP_GEN(dev->mdev, ece_support))
  		resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
  
+ 	if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) &&
+ 	    rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) &&
+ 	    rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format)))
+ 		resp->comp_mask |=
+ 			MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
+ 
  	resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
 +
 +	if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
 +		resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
 +
  	return 0;
  }
  
diff --cc include/uapi/rdma/mlx5-abi.h
index 995faf8f44bd3,82e3bc1eb57df..8597e6f22a1c7
--- a/include/uapi/rdma/mlx5-abi.h
+++ b/include/uapi/rdma/mlx5-abi.h
@@@ -101,7 -101,7 +101,8 @@@ enum mlx5_ib_alloc_ucontext_resp_mask 
  	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
  	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY    = 1UL << 1,
  	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE               = 1UL << 2,
 +	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS           = 1UL << 3,
+ 	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS	   = 1UL << 4,
  };
  
  enum mlx5_user_cmds_supp_uhw {