From: Mark Brown <broonie@kernel.org>
Date: Tue, 20 Jun 2023 14:23:56 +0000 (+0100)
Subject: ASoC: Use maple tree register cache for Everest Semi
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=29735f6fb0f57c8010c9486216361c0f68c90226;p=linux.git

ASoC: Use maple tree register cache for Everest Semi

Merge series from Mark Brown <broonie@kernel.org>:

Several of the Everest Semi CODECs only support single register read and
write operations and therefore do not benefit from using the rbtree
cache over the maple tree cache, convert them to the more modern maple
tree cache.
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29735f6fb0f57c8010c9486216361c0f68c90226