From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: Wed, 21 Apr 2021 18:39:15 +0000 (+0200)
Subject: target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=298d43c96b0f7dc7ea6550ea73b128b3d4ed67f9;p=qemu.git

target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes

Per the nanoMIPS32 Instruction Set Technical Reference Manual,
Revision 01.01, Chapter 3. "Instruction Definitions":

The Read/Write Previous GPR opcodes "require CP0 privilege".

Add the missing CP0 checks.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210421185007.2231855-1-f4bug@amsat.org>
---

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5dad75cdf3..8a0a219742 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -18969,9 +18969,11 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
             }
             break;
         case NM_RDPGPR:
+            check_cp0_enabled(ctx);
             gen_load_srsgpr(rs, rt);
             break;
         case NM_WRPGPR:
+            check_cp0_enabled(ctx);
             gen_store_srsgpr(rs, rt);
             break;
         case NM_WAIT: