From: Marc Zyngier Date: Tue, 15 Aug 2023 18:38:41 +0000 (+0100) Subject: arm64: Add missing BRB/CFP/DVP/CPP instructions X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=2b062ed483ebd625b6c6054b9d29d600bd755a86;p=linux.git arm64: Add missing BRB/CFP/DVP/CPP instructions HFGITR_EL2 traps a bunch of instructions for which we don't have encodings yet. Add them. Reviewed-by: Miguel Luis Reviewed-by: Eric Auger Acked-by: Catalin Marinas Reviewed-by: Jing Zhang Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230815183903.2735724-8-maz@kernel.org --- diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index bb5a0877a210c..6d9d7ac4b31c0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -735,6 +735,13 @@ #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5) #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6) +/* Misc instructions */ +#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4) +#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5) +#define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4) +#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5) +#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7) + /* Common SCTLR_ELx flags. */ #define SCTLR_ELx_ENTP2 (BIT(60)) #define SCTLR_ELx_DSSBS (BIT(44))