From: Matthias Kaehlcke Date: Wed, 10 Apr 2019 18:30:10 +0000 (-0700) Subject: ARM: dts: rockchip: Remove unnecessary setting of UART0 SCLK rate on veyron X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=2f60eb2f03b9c3d0a31592c55a88ef62b1403b5d;p=linux.git ARM: dts: rockchip: Remove unnecessary setting of UART0 SCLK rate on veyron Some veyron devices have a Bluetooth controller connected on UART0. The UART needs to operate at a high speed, however setting the clock rate at initialization has no practical effect. During initialization user space adjusts the UART baudrate multiple times, which ends up changing the SCLK rate. After a successful initiatalization the clk is running at the desired speed (48MHz). Remove the unnecessary clock rate configuration from the DT. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 5181d9435fda6..fa38eb967f12f 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -395,10 +395,6 @@ &uart0 { status = "okay"; - /* We need to go faster than 24MHz, so adjust clock parents / rates */ - assigned-clocks = <&cru SCLK_UART0>; - assigned-clock-rates = <48000000>; - /* Pins don't include flow control by default; add that in */ pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;