From: Yixun Lan <yixun.lan@amlogic.com>
Date: Fri, 19 Jan 2018 02:09:26 +0000 (+0800)
Subject: clk: meson: axg: fix the od shift of the sys_pll
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=2fa9b361e500a0e092a9525afbd6a3a363ffa5f0;p=linux.git

clk: meson: axg: fix the od shift of the sys_pll

According to the datasheet, the od shift of sys_pll is actually 16.

Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[fixed commit message]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index a1ac0ff67e5fb..455d4d8962bb3 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -64,7 +64,7 @@ static struct meson_clk_pll axg_sys_pll = {
 	},
 	.od = {
 		.reg_off = HHI_SYS_PLL_CNTL,
-		.shift   = 10,
+		.shift   = 16,
 		.width   = 2,
 	},
 	.lock = &meson_clk_lock,