From: Thippeswamy Havalige Date: Mon, 16 Oct 2023 05:11:02 +0000 (+0530) Subject: PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=2fccd11518f19571f3802f22d2aad6e72b254c3e;p=linux.git PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses The PCIe Root Port controller expects ECAM size to be set through software. As such, update the value of the NWL_ECAM_VALUE_DEFAULT macro to 16 to allow the controller to address the 256 MB ECAM region and, as such, enable support for detecting up to 256 buses. [kwilczynski: commit log] Link: https://patchwork.kernel.org/project/linux-pci/patch/20231016051102.1180432-5-thippeswamy.havalige@amd.com/ Signed-off-by: Thippeswamy Havalige Signed-off-by: Krzysztof Wilczyński --- diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8fe0e8a325b0b..e307aceba5c97 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_MAX_SIZE 12 +#define NWL_ECAM_MAX_SIZE 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)