From: Jaehyun Chung Date: Sun, 5 Apr 2020 20:41:10 +0000 (-0400) Subject: drm/amd/display: Update DRAM watermark before checking to update TTU X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=2fdcc916ed77e09a0b856b561af8063e93ae96b3;p=linux.git drm/amd/display: Update DRAM watermark before checking to update TTU [Why] In most cases, DRAM watermark is large enough that the result of the condition to increase TTU doesn't change after DRAM watermark is increased. However, there is are cases where the condition fails and becomes true after DRAM watermark is increased. This results in minTTU < DRAM watermarks which leads to PSR hang since p-state is requested but not allowed. [How] Check whether to update TTU after DRAM watermark is updated. Signed-off-by: Jaehyun Chung Reviewed-by: Jun Lei Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index 5bbbafacc7203..922ab7169e524 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -2614,6 +2614,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP if (mode_lib->vba.DRAMClockChangeSupportsVActive && mode_lib->vba.MinActiveDRAMClockChangeMargin > 60) { + mode_lib->vba.DRAMClockChangeWatermark += 25; for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) { @@ -2622,7 +2623,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.MinTTUVBlank[k] += 25; } } - mode_lib->vba.DRAMClockChangeWatermark += 25; + mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; } else if (mode_lib->vba.DummyPStateCheck && mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {