From: Roman Li Date: Wed, 31 Mar 2021 20:50:44 +0000 (-0400) Subject: drm/amd/display: Fix hangs with psr enabled on dcn3.xx X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=2ff3cf8238826b19d604d6a99d9bfcc5ce25081f;p=linux.git drm/amd/display: Fix hangs with psr enabled on dcn3.xx [Why] SKIP_CRTC_DISABLE bit should be applicable to all dcn asics not only Raven. [How] Replace check for Raven only with check for all DCNs. Signed-off-by: Roman Li Acked-by: Bindu Ramamurthy Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index ac7a2b74702ec..9507b08567b40 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -2813,12 +2813,9 @@ bool dc_link_setup_psr(struct dc_link *link, psr_context->psr_level.u32all = 0; -#if defined(CONFIG_DRM_AMD_DC_DCN) /*skip power down the single pipe since it blocks the cstate*/ - if ((link->ctx->asic_id.chip_family == FAMILY_RV) && - ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev)) + if (link->ctx->asic_id.chip_family >= FAMILY_RV) psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; -#endif /* SMU will perform additional powerdown sequence. * For unsupported ASICs, set psr_level flag to skip PSR