From: Linus Walleij <linus.walleij@linaro.org>
Date: Mon, 1 Oct 2018 11:20:45 +0000 (+0200)
Subject: Merge tag 'v4.19-rc6' into devel
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=30aa69e7bd9f7af3574120249eecb3726dcaf737;p=linux.git

Merge tag 'v4.19-rc6' into devel

This is the 4.19-rc6 release

I needed to merge this in because of extensive conflicts in
the MSM and Intel pin control drivers. I know how to resolve
them, so let's do it like this.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---

30aa69e7bd9f7af3574120249eecb3726dcaf737
diff --cc drivers/pinctrl/qcom/pinctrl-msm.c
index 6f02bbdb08654,5d72ffad32c29..0726c8a09065b
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@@ -668,9 -633,32 +668,32 @@@ static void msm_gpio_irq_mask(struct ir
  
  	raw_spin_lock_irqsave(&pctrl->lock, flags);
  
 -	val = readl(pctrl->regs + g->intr_cfg_reg);
 +	val = msm_readl_intr_cfg(pctrl, g);
+ 	/*
+ 	 * There are two bits that control interrupt forwarding to the CPU. The
+ 	 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
+ 	 * latched into the interrupt status register when the hardware detects
+ 	 * an irq that it's configured for (either edge for edge type or level
+ 	 * for level type irq). The 'non-raw' status enable bit causes the
+ 	 * hardware to assert the summary interrupt to the CPU if the latched
+ 	 * status bit is set. There's a bug though, the edge detection logic
+ 	 * seems to have a problem where toggling the RAW_STATUS_EN bit may
+ 	 * cause the status bit to latch spuriously when there isn't any edge
+ 	 * so we can't touch that bit for edge type irqs and we have to keep
+ 	 * the bit set anyway so that edges are latched while the line is masked.
+ 	 *
+ 	 * To make matters more complicated, leaving the RAW_STATUS_EN bit
+ 	 * enabled all the time causes level interrupts to re-latch into the
+ 	 * status register because the level is still present on the line after
+ 	 * we ack it. We clear the raw status enable bit during mask here and
+ 	 * set the bit on unmask so the interrupt can't latch into the hardware
+ 	 * while it's masked.
+ 	 */
+ 	if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
+ 		val &= ~BIT(g->intr_raw_status_bit);
+ 
  	val &= ~BIT(g->intr_enable_bit);
 -	writel(val, pctrl->regs + g->intr_cfg_reg);
 +	msm_writel_intr_cfg(val, pctrl, g);
  
  	clear_bit(d->hwirq, pctrl->enabled_irqs);
  
@@@ -689,9 -677,10 +712,10 @@@ static void msm_gpio_irq_unmask(struct 
  
  	raw_spin_lock_irqsave(&pctrl->lock, flags);
  
 -	val = readl(pctrl->regs + g->intr_cfg_reg);
 +	val = msm_readl_intr_cfg(pctrl, g);
+ 	val |= BIT(g->intr_raw_status_bit);
  	val |= BIT(g->intr_enable_bit);
 -	writel(val, pctrl->regs + g->intr_cfg_reg);
 +	msm_writel_intr_cfg(val, pctrl, g);
  
  	set_bit(d->hwirq, pctrl->enabled_irqs);