From: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
Date: Thu, 2 Feb 2023 09:41:33 +0000 (+0530)
Subject: i2c: xiic: Add wait for FIFO empty in send_tx
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=317b56c9aa9b0b0f4fae738e27998901b7b3b51c;p=linux.git

i2c: xiic: Add wait for FIFO empty in send_tx

If the tx_half_empty interrupt comes first instead of tx_empty,
STOP bit is generated even before all the bytes are transmitted
out on the bus.
STOP bit should be sent only after all the bytes in the FIFO are
transmitted out of the FIFO. So wait until FIFO is empty before sending
the STOP bit.

Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
---

diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index edc64b79e2931..57084696429c2 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -436,6 +436,13 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
 				data |= XIIC_TX_DYN_STOP_MASK;
 			} else {
 				u8 cr;
+				int status;
+
+				/* Wait till FIFO is empty so STOP is sent last */
+				status = xiic_wait_tx_empty(i2c);
+				if (status)
+					return;
+
 				/* Write to CR to stop */
 				cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
 				xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &