From: Matt Roper Date: Wed, 15 Nov 2023 18:30:30 +0000 (-0800) Subject: drm/xe/dg2: Wa_18028616096 now applies to all DG2 X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=32dd40fb48c56265ab08d379fecb8bbf62e3c427;p=linux.git drm/xe/dg2: Wa_18028616096 now applies to all DG2 The workaround database was just updated to extend this workaround to DG2-G11 (whereas previously it applied only to G10 and G12). Reviewed-by: Gustavo Sousa Link: https://lore.kernel.org/r/20231115183029.2649992-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper Signed-off-by: Rodrigo Vivi --- diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index d03e6674519f1..6572715dfc093 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -403,12 +403,7 @@ static const struct xe_rtp_entry_sr engine_was[] = { PERF_FIX_BALANCING_CFE_DISABLE)) }, { XE_RTP_NAME("18028616096"), - XE_RTP_RULES(SUBPLATFORM(DG2, G10), - FUNC(xe_rtp_match_first_render_or_compute)), - XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) - }, - { XE_RTP_NAME("18028616096"), - XE_RTP_RULES(SUBPLATFORM(DG2, G12), + XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) },