From: Frédéric Pétrot Date: Thu, 6 Jan 2022 21:00:54 +0000 (+0100) Subject: target/riscv: additional macros to check instruction support X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=344b4a82fc165798546dbf276c7b281899c177a0;p=qemu.git target/riscv: additional macros to check instruction support Given that the 128-bit version of the riscv spec adds new instructions, and that some instructions that were previously only available in 64-bit mode are now available for both 64-bit and 128-bit, we added new macros to check for the processor mode during translation. Although RV128 is a superset of RV64, we keep for now the RV64 only tests for extensions other than RVI and RVM. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20220106210108.138226-5-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis --- diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5df6c0d800..502bf0d009 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -443,10 +443,22 @@ EX_SH(12) } \ } while (0) -#define REQUIRE_64BIT(ctx) do { \ - if (get_xl(ctx) < MXL_RV64) { \ - return false; \ - } \ +#define REQUIRE_64BIT(ctx) do { \ + if (get_xl(ctx) != MXL_RV64) { \ + return false; \ + } \ +} while (0) + +#define REQUIRE_128BIT(ctx) do { \ + if (get_xl(ctx) != MXL_RV128) { \ + return false; \ + } \ +} while (0) + +#define REQUIRE_64_OR_128BIT(ctx) do { \ + if (get_xl(ctx) == MXL_RV32) { \ + return false; \ + } \ } while (0) static int ex_rvc_register(DisasContext *ctx, int reg)