From: Linus Torvalds Date: Tue, 2 May 2023 22:40:41 +0000 (-0700) Subject: Merge tag 'pinctrl-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw... X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=348551ddaf311c76b01cdcbaf61b6fef06a49144;p=linux.git Merge tag 'pinctrl-v6.4-1' of git://git./linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Mostly drivers! Nothing special: some new Qualcomm chips as usual, and the new NXP S32 and nVidia BlueField-3. Core changes: - Make a lot of pin controllers with GPIO and irqchips immutable, i.e. not living structs, but const structs. This is driving a changed initiated by the irqchip maintainers. New drivers: - New driver for the NXP S32 SoC pin controller - As part of a thorough cleanup and restructuring of the Ralink/Mediatek drivers, the Ralink MIPS pin control drivers were folded into the Mediatek directory and the family is renamed "mtmips". The Ralink chips live on as Mediatek MIPS family where new variants can be added. As part of this work also the device tree bindings were reworked. - New subdriver for the Qualcomm SM7150 SoC. - New subdriver for the Qualcomm IPQ9574 SoC. - New driver for the nVidia BlueField-3 SoC. - Support for the Qualcomm PMM8654AU mixed signal circuit GPIO. - Support for the Qualcomm PMI632 mixed signal circuit GPIO. Improvements: - Add some missing pins and generic cleanups on the Renesas r8a779g0 and r8a779g0 pin controllers. Generic Renesas extension for power source selection on several SoCs. - Misc cleanups for the Atmel AT91 and AT91-PIO4 pin controllers - Make the GPIO mode work on the Qualcomm SM8550-lpass-lpi driver. - Several device tree binding cleanups as the binding YAML syntax is solidifying" * tag 'pinctrl-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (153 commits) pinctrl-bcm2835.c: fix race condition when setting gpio dir dt-bindings: pinctrl: qcom,sm8150: Drop duplicate function value "atest_usb2" dt-bindings: pinctrl: qcom: Add few missing functions pinctrl: qcom: spmi-gpio: Add PMI632 support dt-bindings: pinctrl: qcom,pmic-gpio: add PMI632 pinctrl: wpcm450: select MFD_SYSCON pinctrl: qcom ssbi-gpio: Convert to immutable irq_chip pinctrl: qcom ssbi-mpp: Convert to immutable irq_chip pinctrl: qcom spmi-mpp: Convert to immutable irq_chip pinctrl: plgpio: Convert to immutable irq_chip pinctrl: pistachio: Convert to immutable irq_chip pinctrl: pic32: Convert to immutable irq_chip pinctrl: sx150x: Convert to immutable irq_chip pinctrl: stmfx: Convert to immutable irq_chip pinctrl: st: Convert to immutable irq_chip pinctrl: mcp23s08: Convert to immutable irq_chip pinctrl: equilibrium: Convert to immutable irq_chip pinctrl: npcm7xx: Convert to immutable irq_chip pinctrl: armada-37xx: Convert to immutable irq_chip pinctrl: nsp: Convert to immutable irq_chip ... --- 348551ddaf311c76b01cdcbaf61b6fef06a49144 diff --cc Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml index 0000000000000,c43338cafd610..1686427eb8547 mode 000000,100644..100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@@ -1,0 -1,184 +1,184 @@@ + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + %YAML 1.2 + --- + $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + + title: MediaTek MT8192 Pin Controller + + maintainers: + - Sean Wang + + description: + The MediaTek's MT8192 Pin controller is used to control SoC pins. + + properties: + compatible: + const: mediatek,mt8192-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + description: GPIO valid number range. + maxItems: 1 + + gpio-line-names: true + + reg: + description: + Physical address base for GPIO base registers. There are 11 GPIO physical + address base in mt8192. + maxItems: 11 + + reg-names: + description: + GPIO base register names. + maxItems: 11 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + -#PIN CONFIGURATION NODES ++# PIN CONFIGURATION NODES + patternProperties: + '-pins$': + type: object + additionalProperties: false + patternProperties: + '^pins': + type: object + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: pinmux-node.yaml + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. + + drive-strength: + description: + It can support some arguments, such as MTK_DRIVE_4mA, + MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. It can only + support 2/4/6/8/10/12/14/16mA in mt8192. + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203] + description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203] + description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + + allOf: + - $ref: pinctrl.yaml# + + required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + + additionalProperties: false + + examples: + - | + #include + #include + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c20000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e70000 0x1000>, + <0x11ea0000 0x1000>, + <0x11f20000 0x1000>, + <0x11f30000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + spi1-default-pins { + pins-cs-mosi-clk { + pinmux = , + , + ; + bias-disable; + }; + + pins-miso { + pinmux = ; + bias-pull-down; + }; + }; + }; diff --cc drivers/pinctrl/mediatek/Kconfig index a71874fed3d60,ee04b1af36dd5..7af287252834a --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@@ -40,12 -44,54 +44,54 @@@ config PINCTRL_MTK_PARI select GENERIC_PINCONF select GPIOLIB select EINT_MTK - select OF_GPIO select PINCTRL_MTK_V2 + # For MIPS SoCs + config PINCTRL_MT7620 + bool "MediaTek MT7620 pin control" + depends on SOC_MT7620 || COMPILE_TEST + depends on RALINK + default SOC_MT7620 + select PINCTRL_MTK_MTMIPS + + config PINCTRL_MT7621 + bool "MediaTek MT7621 pin control" + depends on SOC_MT7621 || COMPILE_TEST + depends on RALINK + default SOC_MT7621 + select PINCTRL_MTK_MTMIPS + + config PINCTRL_MT76X8 + bool "MediaTek MT76X8 pin control" + depends on SOC_MT7620 || COMPILE_TEST + depends on RALINK + default SOC_MT7620 + select PINCTRL_MTK_MTMIPS + + config PINCTRL_RT2880 + bool "Ralink RT2880 pin control" + depends on SOC_RT288X || COMPILE_TEST + depends on RALINK + default SOC_RT288X + select PINCTRL_MTK_MTMIPS + + config PINCTRL_RT305X + bool "Ralink RT305X pin control" + depends on SOC_RT305X || COMPILE_TEST + depends on RALINK + default SOC_RT305X + select PINCTRL_MTK_MTMIPS + + config PINCTRL_RT3883 + bool "Ralink RT3883 pin control" + depends on SOC_RT3883 || COMPILE_TEST + depends on RALINK + default SOC_RT3883 + select PINCTRL_MTK_MTMIPS + # For ARMv7 SoCs config PINCTRL_MT2701 - bool "Mediatek MT2701 pin control" + bool "MediaTek MT2701 pin control" depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST depends on OF default MACH_MT2701 diff --cc drivers/pinctrl/pinctrl-at91-pio4.c index c775d239444a6,e40487be20386..2fe40acb6a3e5 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@@ -1202,10 -1197,9 +1197,8 @@@ static int atmel_pinctrl_probe(struct p atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, atmel_pioctrl->gpio_chip->ngpio, &irq_domain_simple_ops, NULL); - if (!atmel_pioctrl->irq_domain) { - dev_err(dev, "can't add the irq domain\n"); - return -ENODEV; - } + if (!atmel_pioctrl->irq_domain) + return dev_err_probe(dev, -ENODEV, "can't add the irq domain\n"); - atmel_pioctrl->irq_domain->name = "atmel gpio"; for (i = 0; i < atmel_pioctrl->npins; i++) { int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);