From: Linus Torvalds Date: Tue, 13 Dec 2022 21:03:06 +0000 (-0800) Subject: Merge tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw... X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=361c89a0da59c04b1d3d33568965fe426b0f18de;p=linux.git Merge tag 'pinctrl-v6.2-1' of git://git./linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "The two large chunks is the header clean-up from Andy and the Qualcomm DT bindings clean-up from Krzysztof. Each which could give rise to conflicts, but I haven't seen any. The YAML conversions happening around the device tree is the biggest item in the series and is the result of Rob Herrings ambition to autovalidate these trees against strict schemas and it is paying off in lots of bugs found and ever prettier device trees. Sooner or later the transition will be complete, Krzysztof is fixing up all of the Qualcomm stuff, which is pretty voluminous. Core changes: - minor but nice and important documentation clean-ups New drivers: - subdriver for the Qualcomm SDM670 SoC - subdriver for the Intel Moorefield SoC - trivial support for the NXP Freescale i.MXRT1170 SoC Other changes and improvements - major clean-up of the Qualcomm pin control device tree bindings by Krzysztof - major header clean-up by Andy - some immutable irqchip clean-up for the Actions Semiconductor and Nuvoton drivers - GPIO helpers for The Cypress cy8c95x0 driver - bias handling in the Mediatek MT7986 driver - remove the unused pins-are-numbered concept that never flew" * tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (231 commits) pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions() dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered dt-bindings: pinctrl: mediatek,mt65xx: Deprecate pins-are-numbered pinctrl: stm32: Remove check for pins-are-numbered pinctrl: mediatek: common: Remove check for pins-are-numbered pinctrl: qcom: remove duplicate included header files pinctrl: sunxi: d1: Add CAN bus pinmuxes pinctrl: loongson2: Fix some const correctness pinctrl: pinconf-generic: add missing of_node_put() pinctrl: intel: Enumerate PWM device when community has a capability pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe() pwm: lpss: Allow other drivers to enable PWM LPSS pwm: lpss: Include headers we are the direct user of pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS pwm: Add a stub for devm_pwmchip_add() pinctrl: k210: call of_node_put() pinctrl: starfive: Use existing variable gpio dt-bindings: pinctrl: semtech,sx150xq: fix match patterns for 16 GPIOs matching pinconf-generic: fix style issues in pin_config_param doc pinctrl: pinctrl-loongson2: fix Kconfig dependency ... --- 361c89a0da59c04b1d3d33568965fe426b0f18de diff --cc MAINTAINERS index fb2686a253424,ded707965944a..3900f24b4dfa5 --- a/MAINTAINERS +++ b/MAINTAINERS @@@ -12086,13 -12004,14 +12086,21 @@@ F: drivers/*/*loongarch F: Documentation/loongarch/ F: Documentation/translations/zh_CN/loongarch/ +LOONGSON-2 SOC SERIES GUTS DRIVER +M: Yinbo Zhu +L: loongarch@lists.linux.dev +S: Maintained +F: Documentation/devicetree/bindings/hwinfo/loongson,ls2k-chipid.yaml +F: drivers/soc/loongson/loongson2_guts.c + + LOONGSON-2 SOC SERIES PINCTRL DRIVER + M: zhanghongchen + M: Yinbo Zhu + L: linux-gpio@vger.kernel.org + S: Maintained + F: Documentation/devicetree/bindings/pinctrl/loongson,ls2k-pinctrl.yaml + F: drivers/pinctrl/pinctrl-loongson2.c + LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) M: Sathya Prakash M: Sreekanth Reddy diff --cc drivers/soc/fsl/qe/gpio.c index 1440922341d82,9abb45ab138b4..1c41eb49d5a77 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@@ -13,11 -13,14 +13,13 @@@ #include #include #include -#include +#include /* for of_mm_gpio_chip */ +#include #include -/* FIXME: needed for gpio_to_chip() get rid of this */ -#include #include #include + #include + #include struct qe_gpio_chip { @@@ -187,16 -181,8 +189,16 @@@ struct qe_pin *qe_pin_request(struct de goto err0; } + qe_pin->controller = gpiochip_get_data(gc); + /* + * FIXME: this gets the local offset on the gpio_chip so that the driver + * can manipulate pin control settings through its custom API. The real + * solution is to create a real pin control driver for this. + */ + qe_pin->num = gpio_num - gc->base; + - if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) { + if (!fwnode_device_is_compatible(gc->fwnode, "fsl,mpc8323-qe-pario-bank")) { - pr_debug("%s: tried to get a non-qe pin\n", __func__); + dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__); err = -EINVAL; goto err0; }