From: Michael Tokarev Date: Tue, 14 Nov 2023 16:09:54 +0000 (+0300) Subject: target/hppa: spelling fixes: Indicies, Truely X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=385b3280ce755448e95d4376d514b3ae001931db;p=qemu.git target/hppa: spelling fixes: Indicies, Truely Fixes: bb67ec32a0bb "target/hppa: Include PSW_P in tb flags and mmu index" Fixes: d7553f3591bb "target/hppa: Populate an interval tree with valid tlb entries" Reviewed-by: Richard Henderson Signed-off-by: Michael Tokarev --- diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index bcfed04f7c..8be45c69c9 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -56,7 +56,7 @@ 1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \ 1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX) -/* Indicies to flush for access_id changes. */ +/* Indices to flush for access_id changes. */ #define HPPA_MMU_FLUSH_P_MASK \ (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \ 1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX) diff --git a/target/hppa/machine.c b/target/hppa/machine.c index 2f8e8cc5a1..15cbc5e6d0 100644 --- a/target/hppa/machine.c +++ b/target/hppa/machine.c @@ -129,7 +129,7 @@ static int tlb_post_load(void *opaque, int version_id) /* * Re-create the interval tree from the valid entries. - * Truely invalid entries should have start == end == 0. + * Truly invalid entries should have start == end == 0. * Otherwise it should be the in-flight tlb_partial entry. */ for (uint32_t i = 0; i < ARRAY_SIZE(env->tlb); ++i) {