From: Palmer Dabbelt Date: Thu, 11 Aug 2022 01:23:51 +0000 (-0700) Subject: riscv: implement Zicbom-based CMO instructions + the t-head variant X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=3aefb2ee5bdd4a8976298415a5a017bf9844bfd5;p=linux.git riscv: implement Zicbom-based CMO instructions + the t-head variant This series is based on the alternatives changes done in my svpbmt series and thus also depends on Atish's isa-extension parsing series. It implements using the cache-management instructions from the Zicbom- extension to handle cache flush, etc actions on platforms needing them. SoCs using cpu cores from T-Head like the Allwinne D1 implement a different set of cache instructions. But while they are different, instructions they provide the same functionality, so a variant can easly hook into the existing alternatives mechanism on those. [Palmer: Some minor fixups, including a RISCV_ISA_ZICBOM dependency on MMU that's probably not strictly necessary. The Zicbom support will trip up sparse for users that have new toolchains, I just sent a patch.] Link: https://lore.kernel.org/all/20220706231536.2041855-1-heiko@sntech.de/ Link: https://lore.kernel.org/linux-sparse/20220811033138.20676-1-palmer@rivosinc.com/T/#u * palmer/riscv-zicbom: riscv: implement cache-management errata for T-Head SoCs riscv: Add support for non-coherent devices using zicbom extension dt-bindings: riscv: document cbom-block-size of: also handle dma-noncoherent in of_dma_is_coherent() --- 3aefb2ee5bdd4a8976298415a5a017bf9844bfd5 diff --cc arch/riscv/Kconfig index 5c52a82e83a88,897ae28abf81e..3d49317f5019b --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@@ -392,6 -385,28 +401,28 @@@ config RISCV_ISA_SVPBM If you don't know what to do here, say Y. + config CC_HAS_ZICBOM + bool + default y if 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicbom) + default y if 32BIT && $(cc-option,-mabi=ilp32 -march=rv32ima_zicbom) + + config RISCV_ISA_ZICBOM + bool "Zicbom extension support for non-coherent DMA operation" + depends on CC_HAS_ZICBOM - depends on !XIP_KERNEL ++ depends on !XIP_KERNEL && MMU + select RISCV_DMA_NONCOHERENT + select RISCV_ALTERNATIVE + default y + help + Adds support to dynamically detect the presence of the ZICBOM + extension (Cache Block Management Operations) and enable its + usage. + + The Zicbom extension can be used to handle for example + non-coherent DMA support on devices that need it. + + If you don't know what to do here, say Y. + config FPU bool "FPU support" default y diff --cc arch/riscv/Kconfig.erratas index f62b62807e853,3223e533fd87f..6850e93899302 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@@ -55,4 -55,15 +55,15 @@@ config ERRATA_THEAD_PBM If you don't know what to do here, say "Y". + config ERRATA_THEAD_CMO + bool "Apply T-Head cache management errata" + depends on ERRATA_THEAD + select RISCV_DMA_NONCOHERENT + default y + help + This will apply the cache management errata to handle the + non-standard handling on non-coherent operations on T-Head SoCs. + + If you don't know what to do here, say "Y". + -endmenu +endmenu # "CPU errata selection" diff --cc arch/riscv/mm/dma-noncoherent.c index 0000000000000,a8dc0bd9078d7..cd2225304c82e mode 000000,100644..100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@@ -1,0 -1,112 +1,116 @@@ + // SPDX-License-Identifier: GPL-2.0-only + /* + * RISC-V specific functions to support DMA for non-coherent devices + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + + #include + #include + #include + #include + #include + #include + + static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES; + static bool noncoherent_supported; + + void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, + enum dma_data_direction dir) + { + void *vaddr = phys_to_virt(paddr); + + switch (dir) { + case DMA_TO_DEVICE: + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + break; + case DMA_FROM_DEVICE: + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + break; + case DMA_BIDIRECTIONAL: + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + break; + default: + break; + } + } + + void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, + enum dma_data_direction dir) + { + void *vaddr = phys_to_virt(paddr); + + switch (dir) { + case DMA_TO_DEVICE: + break; + case DMA_FROM_DEVICE: + case DMA_BIDIRECTIONAL: + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + break; + default: + break; + } + } + + void arch_dma_prep_coherent(struct page *page, size_t size) + { + void *flush_addr = page_address(page); + + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); + } + + void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, + const struct iommu_ops *iommu, bool coherent) + { + WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN, + TAINT_CPU_OUT_OF_SPEC, + "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)", + dev_driver_string(dev), dev_name(dev), + ARCH_DMA_MINALIGN, riscv_cbom_block_size); + + WARN_TAINT(!coherent && !noncoherent_supported, TAINT_CPU_OUT_OF_SPEC, + "%s %s: device non-coherent but no non-coherent operations supported", + dev_driver_string(dev), dev_name(dev)); + + dev->dma_coherent = coherent; + } + + #ifdef CONFIG_RISCV_ISA_ZICBOM + void riscv_init_cbom_blocksize(void) + { + struct device_node *node; + int ret; + u32 val; + + for_each_of_cpu_node(node) { - int hartid = riscv_of_processor_hartid(node); ++ unsigned long hartid; + int cbom_hartid; + ++ ret = riscv_of_processor_hartid(node, &hartid); ++ if (ret) ++ continue; ++ + if (hartid < 0) + continue; + + /* set block-size for cbom extension if available */ + ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); + if (ret) + continue; + + if (!riscv_cbom_block_size) { + riscv_cbom_block_size = val; + cbom_hartid = hartid; + } else { + if (riscv_cbom_block_size != val) - pr_warn("cbom-block-size mismatched between harts %d and %d\n", ++ pr_warn("cbom-block-size mismatched between harts %d and %lu\n", + cbom_hartid, hartid); + } + } + } + #endif + + void riscv_noncoherent_supported(void) + { + noncoherent_supported = true; + }