From: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: Mon, 10 Feb 2025 09:11:16 +0000 (+0100)
Subject: target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=3bbcc0f732a173f164628243c6345b659c08900d;p=qemu.git

target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210133134.90879-5-philmd@linaro.org>
---

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6da391738f..d4f01965df 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3056,7 +3056,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
 {
     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 
-    mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
+    mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data;
     riscv_cpu_validate_misa_mxl(mcc);
 }
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 616c3bdc1c..7de19b4183 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -539,7 +539,7 @@ struct RISCVCPUClass {
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
-    uint32_t misa_mxl_max;  /* max mxl for this cpu */
+    RISCVMXL misa_mxl_max;  /* max mxl for this cpu */
 };
 
 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)