From: Sergey Fedorov <serge.fdrv@gmail.com>
Date: Sun, 26 Apr 2015 15:49:26 +0000 (+0100)
Subject: target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=3d5c84ff21a8a7a3bfb3a75154be8905e62f51db;p=qemu.git

target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled

Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1429669112-29835-1-git-send-email-serge.fdrv@gmail.com
Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 3b5a93dbca..3ca3fa8d21 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -524,9 +524,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         unset_feature(env, ARM_FEATURE_EL3);
 
         /* Disable the security extension feature bits in the processor feature
-         * register as well.  This is id_pfr1[7:4].
+         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
          */
         cpu->id_pfr1 &= ~0xf0;
+        cpu->id_aa64pfr0 &= ~0xf000;
     }
 
     register_cp_regs_for_features(cpu);