From: Jani Nikula Date: Fri, 24 Jan 2020 13:25:46 +0000 (+0200) Subject: drm/i915/pipe_crc: use intel_de_*() functions for register access X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=41dd67c13086ddb725f8e11e49474e781af90546;p=linux.git drm/i915/pipe_crc: use intel_de_*() functions for register access The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Acked-by: Chris Wilson Acked-by: Rodrigo Vivi Acked-by: Joonas Lahtinen Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/0af05f6035046a515097da398de8722c0ca23e56.1579871655.git.jani.nikula@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 520408e83681b..b83062201212d 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -172,7 +172,7 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, * - DisplayPort scrambling: used for EMI reduction */ if (need_stable_symbols) { - u32 tmp = I915_READ(PORT_DFT2_G4X); + u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X); tmp |= DC_BALANCE_RESET_VLV; switch (pipe) { @@ -188,7 +188,7 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, default: return -EINVAL; } - I915_WRITE(PORT_DFT2_G4X, tmp); + intel_de_write(dev_priv, PORT_DFT2_G4X, tmp); } return 0; @@ -237,7 +237,7 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, enum pipe pipe) { - u32 tmp = I915_READ(PORT_DFT2_G4X); + u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X); switch (pipe) { case PIPE_A: @@ -254,7 +254,7 @@ static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, } if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) tmp &= ~DC_BALANCE_RESET_VLV; - I915_WRITE(PORT_DFT2_G4X, tmp); + intel_de_write(dev_priv, PORT_DFT2_G4X, tmp); } static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, @@ -615,8 +615,8 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name) goto out; pipe_crc->source = source; - I915_WRITE(PIPE_CRC_CTL(crtc->index), val); - POSTING_READ(PIPE_CRC_CTL(crtc->index)); + intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), val); + intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index)); if (!source) { if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) @@ -650,8 +650,8 @@ void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc) /* Don't need pipe_crc->lock here, IRQs are not generated. */ pipe_crc->skipped = 0; - I915_WRITE(PIPE_CRC_CTL(crtc->index), val); - POSTING_READ(PIPE_CRC_CTL(crtc->index)); + intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), val); + intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index)); } void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc) @@ -665,7 +665,7 @@ void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc) pipe_crc->skipped = INT_MIN; spin_unlock_irq(&pipe_crc->lock); - I915_WRITE(PIPE_CRC_CTL(crtc->index), 0); - POSTING_READ(PIPE_CRC_CTL(crtc->index)); + intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), 0); + intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index)); intel_synchronize_irq(dev_priv); }