From: Gayatri Kammela Date: Sat, 17 Apr 2021 03:12:51 +0000 (-0700) Subject: platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=43ef6c226a60b1c52890791af73f7015f68a315a;p=linux.git platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information and supports a few additional registers. Hence add the LTR registers specific to Tiger Lake to the cnp_ltr_show_map[]. Also adjust the number of LTR IPs for Tiger Lake to the correct amount. Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Hans de Goede Acked-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20210417031252.3020837-9-david.e.box@linux.intel.com Signed-off-by: Hans de Goede --- diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 5240eefe8e6e4..6e5ad5de9b211 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -383,6 +383,8 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = { * a list of core SoCs using this. */ {"WIGIG", ICL_PMC_LTR_WIGIG}, + {"THC0", TGL_PMC_LTR_THC0}, + {"THC1", TGL_PMC_LTR_THC1}, /* Below two cannot be used for LTR_IGNORE */ {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index c45805671c4a0..e8dae9c6c45fb 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -191,8 +191,10 @@ enum ppfear_regs { #define GET_X2_COUNTER(v) ((v) >> 1) #define LPM_STS_LATCH_MODE BIT(31) -#define TGL_NUM_IP_IGN_ALLOWED 22 #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A +#define TGL_PMC_LTR_THC0 0x1C04 +#define TGL_PMC_LTR_THC1 0x1C08 +#define TGL_NUM_IP_IGN_ALLOWED 23 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ /*