From: Alex Bennée Date: Mon, 15 Jul 2019 13:17:02 +0000 (+0100) Subject: target/arm: report ARMv8-A FP support for AArch32 -cpu max X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=45b1a243b81a7c9ae56235937280711dd9914ca7;p=qemu.git target/arm: report ARMv8-A FP support for AArch32 -cpu max When we converted to using feature bits in 602f6e42cfbf we missed out the fact (dp && arm_dc_feature(s, ARM_FEATURE_V8)) was supported for -cpu max configurations. This caused a regression in the GCC test suite. Fix this by setting the appropriate bits in mvfr1.FPHP to report ARMv8-A with FP support (but not ARMv8.2-FP16). Fixes: https://bugs.launchpad.net/qemu/+bug/1836078 Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20190711103737.10017-1-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e75a64a25a..ad164a773b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2452,6 +2452,10 @@ static void arm_max_initfn(Object *obj) t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 = t; + t = cpu->isar.mvfr1; + t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ + cpu->isar.mvfr1 = t; + t = cpu->isar.mvfr2; t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */