From: Mark Cave-Ayland Date: Wed, 4 May 2022 09:25:52 +0000 (+0100) Subject: lasi: move from hw/hppa to hw/misc X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=45f569a11666051f98edc678616d135c9feaf506;p=qemu.git lasi: move from hw/hppa to hw/misc Move the LASI device implementation from hw/hppa to hw/misc so that it is located with all the other miscellaneous devices. Signed-off-by: Mark Cave-Ayland Acked-by: Helge Deller Message-Id: <20220504092600.10048-43-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland --- diff --git a/MAINTAINERS b/MAINTAINERS index 59210b093a..662ec47246 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1113,7 +1113,9 @@ S: Odd Fixes F: configs/devices/hppa-softmmu/default.mak F: hw/hppa/ F: hw/net/*i82596* +F: hw/misc/lasi.c F: hw/pci-host/dino.c +F: include/hw/misc/lasi.h F: include/hw/net/lasi_82596.h F: include/hw/pci-host/dino.h F: pc-bios/hppa-firmware.img diff --git a/hw/hppa/Kconfig b/hw/hppa/Kconfig index 724380ecec..5dd8b5b21e 100644 --- a/hw/hppa/Kconfig +++ b/hw/hppa/Kconfig @@ -4,6 +4,7 @@ config HPPA_B160L imply E1000_PCI imply VIRTIO_VGA select DINO + select LASI select SERIAL select ISA_BUS select I8259 diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c deleted file mode 100644 index 5ef36f3f58..0000000000 --- a/hw/hppa/lasi.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * HP-PARISC Lasi chipset emulation. - * - * (C) 2019 by Helge Deller - * - * This work is licensed under the GNU GPL license version 2 or later. - * - * Documentation available at: - * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf - */ - -#include "qemu/osdep.h" -#include "qemu/units.h" -#include "qemu/log.h" -#include "qapi/error.h" -#include "trace.h" -#include "hw/irq.h" -#include "sysemu/sysemu.h" -#include "sysemu/runstate.h" -#include "hppa_sys.h" -#include "migration/vmstate.h" -#include "qom/object.h" -#include "lasi.h" - - -static bool lasi_chip_mem_valid(void *opaque, hwaddr addr, - unsigned size, bool is_write, - MemTxAttrs attrs) -{ - bool ret = false; - - switch (addr) { - case LASI_IRR: - case LASI_IMR: - case LASI_IPR: - case LASI_ICR: - case LASI_IAR: - - case LASI_LPT: - case LASI_UART: - case LASI_LAN: - case LASI_RTC: - - case LASI_PCR ... LASI_AMR: - ret = true; - } - - trace_lasi_chip_mem_valid(addr, ret); - return ret; -} - -static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr, - uint64_t *data, unsigned size, - MemTxAttrs attrs) -{ - LasiState *s = opaque; - MemTxResult ret = MEMTX_OK; - uint32_t val; - - switch (addr) { - case LASI_IRR: - val = s->irr; - break; - case LASI_IMR: - val = s->imr; - break; - case LASI_IPR: - val = s->ipr; - /* Any read to IPR clears the register. */ - s->ipr = 0; - break; - case LASI_ICR: - val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */ - break; - case LASI_IAR: - val = s->iar; - break; - - case LASI_LPT: - case LASI_UART: - case LASI_LAN: - val = 0; - break; - case LASI_RTC: - val = time(NULL); - val += s->rtc_ref; - break; - - case LASI_PCR: - case LASI_VER: /* only version 0 existed. */ - case LASI_IORESET: - val = 0; - break; - case LASI_ERRLOG: - val = s->errlog; - break; - case LASI_AMR: - val = s->amr; - break; - - default: - /* Controlled by lasi_chip_mem_valid above. */ - g_assert_not_reached(); - } - - trace_lasi_chip_read(addr, val); - - *data = val; - return ret; -} - -static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - LasiState *s = opaque; - - trace_lasi_chip_write(addr, val); - - switch (addr) { - case LASI_IRR: - /* read-only. */ - break; - case LASI_IMR: - s->imr = val; - if (((val & LASI_IRQ_BITS) != val) && (val != 0xffffffff)) { - qemu_log_mask(LOG_GUEST_ERROR, - "LASI: tried to set invalid %lx IMR value.\n", - (unsigned long) val); - } - break; - case LASI_IPR: - /* Any write to IPR clears the register. */ - s->ipr = 0; - break; - case LASI_ICR: - s->icr = val; - /* if (val & ICR_TOC_BIT) issue_toc(); */ - break; - case LASI_IAR: - s->iar = val; - break; - - case LASI_LPT: - /* XXX: reset parallel port */ - break; - case LASI_UART: - /* XXX: reset serial port */ - break; - case LASI_LAN: - /* XXX: reset LAN card */ - break; - case LASI_RTC: - s->rtc_ref = val - time(NULL); - break; - - case LASI_PCR: - if (val == 0x02) { /* immediately power off */ - qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); - } - break; - case LASI_ERRLOG: - s->errlog = val; - break; - case LASI_VER: - /* read-only. */ - break; - case LASI_IORESET: - break; /* XXX: TODO: Reset various devices. */ - case LASI_AMR: - s->amr = val; - break; - - default: - /* Controlled by lasi_chip_mem_valid above. */ - g_assert_not_reached(); - } - return MEMTX_OK; -} - -static const MemoryRegionOps lasi_chip_ops = { - .read_with_attrs = lasi_chip_read_with_attrs, - .write_with_attrs = lasi_chip_write_with_attrs, - .endianness = DEVICE_BIG_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 4, - .accepts = lasi_chip_mem_valid, - }, - .impl = { - .min_access_size = 1, - .max_access_size = 4, - }, -}; - -static const VMStateDescription vmstate_lasi = { - .name = "Lasi", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT32(irr, LasiState), - VMSTATE_UINT32(imr, LasiState), - VMSTATE_UINT32(ipr, LasiState), - VMSTATE_UINT32(icr, LasiState), - VMSTATE_UINT32(iar, LasiState), - VMSTATE_UINT32(errlog, LasiState), - VMSTATE_UINT32(amr, LasiState), - VMSTATE_END_OF_LIST() - } -}; - - -static void lasi_set_irq(void *opaque, int irq, int level) -{ - LasiState *s = opaque; - uint32_t bit = 1u << irq; - - if (level) { - s->ipr |= bit; - if (bit & s->imr) { - uint32_t iar = s->iar; - s->irr |= bit; - if ((s->icr & ICR_BUS_ERROR_BIT) == 0) { - stl_be_phys(&address_space_memory, iar & -32, iar & 31); - } - } - } -} - -static void lasi_reset(DeviceState *dev) -{ - LasiState *s = LASI_CHIP(dev); - - s->iar = 0xFFFB0000 + 3; /* CPU_HPA + 3 */ - - /* Real time clock (RTC), it's only one 32-bit counter @9000 */ - s->rtc = time(NULL); - s->rtc_ref = 0; -} - -static void lasi_init(Object *obj) -{ - LasiState *s = LASI_CHIP(obj); - SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - - memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops, - s, "lasi", 0x100000); - - sysbus_init_mmio(sbd, &s->this_mem); - - qdev_init_gpio_in(DEVICE(obj), lasi_set_irq, LASI_IRQS); -} - -static void lasi_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->reset = lasi_reset; - dc->vmsd = &vmstate_lasi; -} - -static const TypeInfo lasi_pcihost_info = { - .name = TYPE_LASI_CHIP, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_init = lasi_init, - .instance_size = sizeof(LasiState), - .class_init = lasi_class_init, -}; - -static void lasi_register_types(void) -{ - type_register_static(&lasi_pcihost_info); -} - -type_init(lasi_register_types) diff --git a/hw/hppa/lasi.h b/hw/hppa/lasi.h deleted file mode 100644 index ecc7065ce8..0000000000 --- a/hw/hppa/lasi.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * HP-PARISC Lasi chipset emulation. - * - * (C) 2019 by Helge Deller - * - * This work is licensed under the GNU GPL license version 2 or later. - * - * Documentation available at: - * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf - */ - -#ifndef LASI_H -#define LASI_H - -#include "exec/address-spaces.h" -#include "hw/pci/pci_host.h" -#include "hw/boards.h" - -#define TYPE_LASI_CHIP "lasi-chip" -OBJECT_DECLARE_SIMPLE_TYPE(LasiState, LASI_CHIP) - -#define LASI_IRR 0x00 /* RO */ -#define LASI_IMR 0x04 -#define LASI_IPR 0x08 -#define LASI_ICR 0x0c -#define LASI_IAR 0x10 - -#define LASI_LPT 0x02000 -#define LASI_UART 0x05000 -#define LASI_LAN 0x07000 -#define LASI_RTC 0x09000 - -#define LASI_PCR 0x0C000 /* LASI Power Control register */ -#define LASI_ERRLOG 0x0C004 /* LASI Error Logging register */ -#define LASI_VER 0x0C008 /* LASI Version Control register */ -#define LASI_IORESET 0x0C00C /* LASI I/O Reset register */ -#define LASI_AMR 0x0C010 /* LASI Arbitration Mask register */ -#define LASI_IO_CONF 0x7FFFE /* LASI primary configuration register */ -#define LASI_IO_CONF2 0x7FFFF /* LASI secondary configuration register */ - -#define LASI_BIT(x) (1ul << (x)) -#define LASI_IRQ_BITS (LASI_BIT(5) | LASI_BIT(7) | LASI_BIT(8) | LASI_BIT(9) \ - | LASI_BIT(13) | LASI_BIT(14) | LASI_BIT(16) | LASI_BIT(17) \ - | LASI_BIT(18) | LASI_BIT(19) | LASI_BIT(20) | LASI_BIT(21) \ - | LASI_BIT(26)) - -#define ICR_BUS_ERROR_BIT LASI_BIT(8) /* bit 8 in ICR */ -#define ICR_TOC_BIT LASI_BIT(1) /* bit 1 in ICR */ - -#define LASI_IRQS 27 - -#define LASI_IRQ_HPA 14 -#define LASI_IRQ_UART_HPA 5 -#define LASI_IRQ_LPT_HPA 7 -#define LASI_IRQ_LAN_HPA 8 -#define LASI_IRQ_SCSI_HPA 9 -#define LASI_IRQ_AUDIO_HPA 13 -#define LASI_IRQ_PS2KBD_HPA 26 -#define LASI_IRQ_PS2MOU_HPA 26 - -struct LasiState { - PCIHostState parent_obj; - - uint32_t irr; - uint32_t imr; - uint32_t ipr; - uint32_t icr; - uint32_t iar; - - uint32_t errlog; - uint32_t amr; - uint32_t rtc; - time_t rtc_ref; - - MemoryRegion this_mem; -}; - -#endif diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 9d904b7a60..f3d72b4c35 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -22,7 +22,7 @@ #include "hw/nmi.h" #include "hw/pci/pci.h" #include "hw/pci-host/dino.h" -#include "lasi.h" +#include "hw/misc/lasi.h" #include "hppa_sys.h" #include "qemu/units.h" #include "qapi/error.h" diff --git a/hw/hppa/meson.build b/hw/hppa/meson.build index a6f9db455c..bd5a1fb1d2 100644 --- a/hw/hppa/meson.build +++ b/hw/hppa/meson.build @@ -1,4 +1,4 @@ hppa_ss = ss.source_set() -hppa_ss.add(when: 'CONFIG_HPPA_B160L', if_true: files('pci.c', 'machine.c', 'lasi.c')) +hppa_ss.add(when: 'CONFIG_HPPA_B160L', if_true: files('pci.c', 'machine.c')) hw_arch += {'hppa': hppa_ss} diff --git a/hw/hppa/trace-events b/hw/hppa/trace-events index 871a473771..1a4fbe2fa8 100644 --- a/hw/hppa/trace-events +++ b/hw/hppa/trace-events @@ -2,8 +2,3 @@ # pci.c hppa_pci_iack_write(void) "" - -# lasi.c -lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" -lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" -lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 507058d8bf..cbabe9f78c 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -171,4 +171,7 @@ config SIFIVE_U_PRCI config VIRT_CTRL bool +config LASI + bool + source macio/Kconfig diff --git a/hw/misc/lasi.c b/hw/misc/lasi.c new file mode 100644 index 0000000000..23a7634a8c --- /dev/null +++ b/hw/misc/lasi.c @@ -0,0 +1,274 @@ +/* + * HP-PARISC Lasi chipset emulation. + * + * (C) 2019 by Helge Deller + * + * This work is licensed under the GNU GPL license version 2 or later. + * + * Documentation available at: + * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "trace.h" +#include "hw/irq.h" +#include "sysemu/sysemu.h" +#include "sysemu/runstate.h" +#include "migration/vmstate.h" +#include "qom/object.h" +#include "hw/misc/lasi.h" + + +static bool lasi_chip_mem_valid(void *opaque, hwaddr addr, + unsigned size, bool is_write, + MemTxAttrs attrs) +{ + bool ret = false; + + switch (addr) { + case LASI_IRR: + case LASI_IMR: + case LASI_IPR: + case LASI_ICR: + case LASI_IAR: + + case LASI_LPT: + case LASI_UART: + case LASI_LAN: + case LASI_RTC: + + case LASI_PCR ... LASI_AMR: + ret = true; + } + + trace_lasi_chip_mem_valid(addr, ret); + return ret; +} + +static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + LasiState *s = opaque; + MemTxResult ret = MEMTX_OK; + uint32_t val; + + switch (addr) { + case LASI_IRR: + val = s->irr; + break; + case LASI_IMR: + val = s->imr; + break; + case LASI_IPR: + val = s->ipr; + /* Any read to IPR clears the register. */ + s->ipr = 0; + break; + case LASI_ICR: + val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */ + break; + case LASI_IAR: + val = s->iar; + break; + + case LASI_LPT: + case LASI_UART: + case LASI_LAN: + val = 0; + break; + case LASI_RTC: + val = time(NULL); + val += s->rtc_ref; + break; + + case LASI_PCR: + case LASI_VER: /* only version 0 existed. */ + case LASI_IORESET: + val = 0; + break; + case LASI_ERRLOG: + val = s->errlog; + break; + case LASI_AMR: + val = s->amr; + break; + + default: + /* Controlled by lasi_chip_mem_valid above. */ + g_assert_not_reached(); + } + + trace_lasi_chip_read(addr, val); + + *data = val; + return ret; +} + +static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LasiState *s = opaque; + + trace_lasi_chip_write(addr, val); + + switch (addr) { + case LASI_IRR: + /* read-only. */ + break; + case LASI_IMR: + s->imr = val; + if (((val & LASI_IRQ_BITS) != val) && (val != 0xffffffff)) { + qemu_log_mask(LOG_GUEST_ERROR, + "LASI: tried to set invalid %lx IMR value.\n", + (unsigned long) val); + } + break; + case LASI_IPR: + /* Any write to IPR clears the register. */ + s->ipr = 0; + break; + case LASI_ICR: + s->icr = val; + /* if (val & ICR_TOC_BIT) issue_toc(); */ + break; + case LASI_IAR: + s->iar = val; + break; + + case LASI_LPT: + /* XXX: reset parallel port */ + break; + case LASI_UART: + /* XXX: reset serial port */ + break; + case LASI_LAN: + /* XXX: reset LAN card */ + break; + case LASI_RTC: + s->rtc_ref = val - time(NULL); + break; + + case LASI_PCR: + if (val == 0x02) { /* immediately power off */ + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } + break; + case LASI_ERRLOG: + s->errlog = val; + break; + case LASI_VER: + /* read-only. */ + break; + case LASI_IORESET: + break; /* XXX: TODO: Reset various devices. */ + case LASI_AMR: + s->amr = val; + break; + + default: + /* Controlled by lasi_chip_mem_valid above. */ + g_assert_not_reached(); + } + return MEMTX_OK; +} + +static const MemoryRegionOps lasi_chip_ops = { + .read_with_attrs = lasi_chip_read_with_attrs, + .write_with_attrs = lasi_chip_write_with_attrs, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + .accepts = lasi_chip_mem_valid, + }, + .impl = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +static const VMStateDescription vmstate_lasi = { + .name = "Lasi", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(irr, LasiState), + VMSTATE_UINT32(imr, LasiState), + VMSTATE_UINT32(ipr, LasiState), + VMSTATE_UINT32(icr, LasiState), + VMSTATE_UINT32(iar, LasiState), + VMSTATE_UINT32(errlog, LasiState), + VMSTATE_UINT32(amr, LasiState), + VMSTATE_END_OF_LIST() + } +}; + + +static void lasi_set_irq(void *opaque, int irq, int level) +{ + LasiState *s = opaque; + uint32_t bit = 1u << irq; + + if (level) { + s->ipr |= bit; + if (bit & s->imr) { + uint32_t iar = s->iar; + s->irr |= bit; + if ((s->icr & ICR_BUS_ERROR_BIT) == 0) { + stl_be_phys(&address_space_memory, iar & -32, iar & 31); + } + } + } +} + +static void lasi_reset(DeviceState *dev) +{ + LasiState *s = LASI_CHIP(dev); + + s->iar = 0xFFFB0000 + 3; /* CPU_HPA + 3 */ + + /* Real time clock (RTC), it's only one 32-bit counter @9000 */ + s->rtc = time(NULL); + s->rtc_ref = 0; +} + +static void lasi_init(Object *obj) +{ + LasiState *s = LASI_CHIP(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops, + s, "lasi", 0x100000); + + sysbus_init_mmio(sbd, &s->this_mem); + + qdev_init_gpio_in(DEVICE(obj), lasi_set_irq, LASI_IRQS); +} + +static void lasi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = lasi_reset; + dc->vmsd = &vmstate_lasi; +} + +static const TypeInfo lasi_pcihost_info = { + .name = TYPE_LASI_CHIP, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = lasi_init, + .instance_size = sizeof(LasiState), + .class_init = lasi_class_init, +}; + +static void lasi_register_types(void) +{ + type_register_static(&lasi_pcihost_info); +} + +type_init(lasi_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 2ff05c7afa..132b7b7344 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -134,3 +134,6 @@ specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cp specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c')) specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c')) + +# HPPA devices +softmmu_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c')) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 4e0c7973a4..c5e37b0154 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -263,3 +263,8 @@ virt_ctrl_write(void *dev, unsigned int addr, unsigned int size, uint64_t value) virt_ctrl_reset(void *dev) "ctrl: %p" virt_ctrl_realize(void *dev) "ctrl: %p" virt_ctrl_instance_init(void *dev) "ctrl: %p" + +# lasi.c +lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" +lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" +lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" diff --git a/include/hw/misc/lasi.h b/include/hw/misc/lasi.h new file mode 100644 index 0000000000..ecc7065ce8 --- /dev/null +++ b/include/hw/misc/lasi.h @@ -0,0 +1,78 @@ +/* + * HP-PARISC Lasi chipset emulation. + * + * (C) 2019 by Helge Deller + * + * This work is licensed under the GNU GPL license version 2 or later. + * + * Documentation available at: + * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf + */ + +#ifndef LASI_H +#define LASI_H + +#include "exec/address-spaces.h" +#include "hw/pci/pci_host.h" +#include "hw/boards.h" + +#define TYPE_LASI_CHIP "lasi-chip" +OBJECT_DECLARE_SIMPLE_TYPE(LasiState, LASI_CHIP) + +#define LASI_IRR 0x00 /* RO */ +#define LASI_IMR 0x04 +#define LASI_IPR 0x08 +#define LASI_ICR 0x0c +#define LASI_IAR 0x10 + +#define LASI_LPT 0x02000 +#define LASI_UART 0x05000 +#define LASI_LAN 0x07000 +#define LASI_RTC 0x09000 + +#define LASI_PCR 0x0C000 /* LASI Power Control register */ +#define LASI_ERRLOG 0x0C004 /* LASI Error Logging register */ +#define LASI_VER 0x0C008 /* LASI Version Control register */ +#define LASI_IORESET 0x0C00C /* LASI I/O Reset register */ +#define LASI_AMR 0x0C010 /* LASI Arbitration Mask register */ +#define LASI_IO_CONF 0x7FFFE /* LASI primary configuration register */ +#define LASI_IO_CONF2 0x7FFFF /* LASI secondary configuration register */ + +#define LASI_BIT(x) (1ul << (x)) +#define LASI_IRQ_BITS (LASI_BIT(5) | LASI_BIT(7) | LASI_BIT(8) | LASI_BIT(9) \ + | LASI_BIT(13) | LASI_BIT(14) | LASI_BIT(16) | LASI_BIT(17) \ + | LASI_BIT(18) | LASI_BIT(19) | LASI_BIT(20) | LASI_BIT(21) \ + | LASI_BIT(26)) + +#define ICR_BUS_ERROR_BIT LASI_BIT(8) /* bit 8 in ICR */ +#define ICR_TOC_BIT LASI_BIT(1) /* bit 1 in ICR */ + +#define LASI_IRQS 27 + +#define LASI_IRQ_HPA 14 +#define LASI_IRQ_UART_HPA 5 +#define LASI_IRQ_LPT_HPA 7 +#define LASI_IRQ_LAN_HPA 8 +#define LASI_IRQ_SCSI_HPA 9 +#define LASI_IRQ_AUDIO_HPA 13 +#define LASI_IRQ_PS2KBD_HPA 26 +#define LASI_IRQ_PS2MOU_HPA 26 + +struct LasiState { + PCIHostState parent_obj; + + uint32_t irr; + uint32_t imr; + uint32_t ipr; + uint32_t icr; + uint32_t iar; + + uint32_t errlog; + uint32_t amr; + uint32_t rtc; + time_t rtc_ref; + + MemoryRegion this_mem; +}; + +#endif