From: Thomas Bogendoerfer Date: Wed, 7 Oct 2020 10:17:04 +0000 (+0200) Subject: MIPS: SGI-IP28: disable use of ll/sc in kernel X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=46dd40aa376c8158b6aa17510079caf5c3af6237;p=linux.git MIPS: SGI-IP28: disable use of ll/sc in kernel SGI-IP28 systems only use broken R10k rev 2.5 CPUs, which could lock up, if ll/sc sequences are issued in certain order. Since those systems are all non-SMP, we can disable ll/sc usage in kernel. Signed-off-by: Thomas Bogendoerfer --- diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h index ba8b4e30b3e27..613bbc10c1f25 100644 --- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h @@ -25,7 +25,7 @@ #define cpu_has_mcheck 0 #define cpu_has_ejtag 0 -#define cpu_has_llsc 1 +#define cpu_has_llsc 0 #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 /* see probe_pcache() */ #define cpu_has_ic_fills_f_dc 0