From: Paolo Bonzini <pbonzini@redhat.com>
Date: Wed, 26 Apr 2023 19:53:36 +0000 (-0400)
Subject: Merge tag 'kvm-x86-pmu-6.4' of https://github.com/kvm-x86/linux into HEAD
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=48b1893ae38bd6d46a9dcfc7b85c70a143fb8cab;p=linux.git

Merge tag 'kvm-x86-pmu-6.4' of https://github.com/kvm-x86/linux into HEAD

KVM x86 PMU changes for 6.4:

 - Disallow virtualizing legacy LBRs if architectural LBRs are available,
   the two are mutually exclusive in hardware

 - Disallow writes to immutable feature MSRs (notably PERF_CAPABILITIES)
   after KVM_RUN, and overhaul the vmx_pmu_caps selftest to better
   validate PERF_CAPABILITIES

 - Apply PMU filters to emulated events and add test coverage to the
   pmu_event_filter selftest

 - Misc cleanups and fixes
---

48b1893ae38bd6d46a9dcfc7b85c70a143fb8cab
diff --cc arch/x86/kvm/x86.c
index ad4a45d8975b9,a86ad45a53b88..095a41c6f3467
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@@ -3627,32 -3632,17 +3645,40 @@@ int kvm_set_msr_common(struct kvm_vcpu 
  		if (data & ~kvm_caps.supported_perf_cap)
  			return 1;
  
+ 		/*
+ 		 * Note, this is not just a performance optimization!  KVM
+ 		 * disallows changing feature MSRs after the vCPU has run; PMU
+ 		 * refresh will bug the VM if called after the vCPU has run.
+ 		 */
+ 		if (vcpu->arch.perf_capabilities == data)
+ 			break;
+ 
  		vcpu->arch.perf_capabilities = data;
  		kvm_pmu_refresh(vcpu);
- 		return 0;
+ 		break;
 +	case MSR_IA32_PRED_CMD:
 +		if (!msr_info->host_initiated && !guest_has_pred_cmd_msr(vcpu))
 +			return 1;
 +
 +		if (!boot_cpu_has(X86_FEATURE_IBPB) || (data & ~PRED_CMD_IBPB))
 +			return 1;
 +		if (!data)
 +			break;
 +
 +		wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
 +		break;
 +	case MSR_IA32_FLUSH_CMD:
 +		if (!msr_info->host_initiated &&
 +		    !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D))
 +			return 1;
 +
 +		if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH))
 +			return 1;
 +		if (!data)
 +			break;
 +
 +		wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
 +		break;
  	case MSR_EFER:
  		return set_efer(vcpu, msr_info);
  	case MSR_K7_HWCR: