From: Philippe Mathieu-Daudé Date: Sun, 3 Oct 2021 14:17:11 +0000 (+0200) Subject: target/ppc: Use tcg_constant_i64() in gen_brh() X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=491b3cca3653bf36db67f91be0e3db64682bef91;p=qemu.git target/ppc: Use tcg_constant_i64() in gen_brh() The mask of the Byte-Reverse Halfword opcode is a read-only constant. We can avoid using a TCG temporary by moving the mask to the constant pool. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211003141711.3673181-3-f4bug@amsat.org> Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0258c1be16..98f304302e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7569,18 +7569,16 @@ static void gen_brw(DisasContext *ctx) /* brh */ static void gen_brh(DisasContext *ctx) { - TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); - tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); - tcg_gen_and_i64(t2, t1, t0); - tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); + tcg_gen_and_i64(t2, t1, mask); + tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); tcg_gen_shli_i64(t1, t1, 8); tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); - tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); tcg_temp_free_i64(t2); }