From: Bhavya Kapoor Date: Fri, 1 Dec 2023 08:20:44 +0000 (+0530) Subject: arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=4a52a8208568a85b0d51e5ca81be5925973ef108;p=linux.git arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for MMCSD High Speed DDR which is DDR50 speed mode for J721s2 SoC according to datasheet for J721s2. [+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in J721s2 datasheet - https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf Signed-off-by: Bhavya Kapoor Reviewed-by: Judith Mendez Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20231201082045.790478-3-b-kapoor@ti.com Signed-off-by: Nishanth Menon --- diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index bf959312fad0d..ea7f2b2ab165d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -766,6 +766,7 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent;