From: Palmer Dabbelt <palmer@rivosinc.com>
Date: Wed, 15 Mar 2023 14:11:08 +0000 (-0700)
Subject: Merge patch series "RISC-V: Apply Zicboz to clear_page"
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=4b740779ac03f42866059a33f5454e1ac5393cdd;p=linux.git

Merge patch series "RISC-V: Apply Zicboz to clear_page"

Andrew Jones <ajones@ventanamicro.com> says:

When the Zicboz extension is available we can more rapidly zero naturally
aligned Zicboz block sized chunks of memory. As pages are always page
aligned and are larger than any Zicboz block size will be, then
clear_page() appears to be a good candidate for the extension. While cycle
count and energy consumption should also be considered, we can be pretty
certain that implementing clear_page() with the Zicboz extension is a win
by comparing the new dynamic instruction count with its current count[1].
Doing so we see that the new count is just over a quarter of the old count
(see patch6's commit message for more details).

For those of you who reviewed v1[2], you may be looking for the memset()
patches. As pointed out in v1, and a couple follow-up emails, it's not
clear that patching memset() is a win yet. When I get a chance to test
on real hardware with a comprehensive benchmark collection then I can
post the memset() patches separately (assuming the benchmarks show it's
worthwhile).

* b4-shazam-merge:
  RISC-V: KVM: Expose Zicboz to the guest
  RISC-V: KVM: Provide UAPI for Zicboz block size
  RISC-V: Use Zicboz in clear_page when available
  RISC-V: cpufeatures: Put the upper 16 bits of patch ID to work
  RISC-V: Add Zicboz detection and block size parsing
  dt-bindings: riscv: Document cboz-block-size
  RISC-V: Factor out body of riscv_init_cbom_blocksize loop
  RISC-V: alternatives: Support patching multiple insns in assembly

Link: https://lore.kernel.org/r/20230224162631.405473-1-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---

4b740779ac03f42866059a33f5454e1ac5393cdd
diff --cc arch/riscv/include/asm/hwcap.h
index 0ed15c2a28166,5955fbeaba86b..bbde5aafa9573
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@@ -42,7 -42,7 +42,8 @@@
  #define RISCV_ISA_EXT_ZBB		30
  #define RISCV_ISA_EXT_ZICBOM		31
  #define RISCV_ISA_EXT_ZIHINTPAUSE	32
 -#define RISCV_ISA_EXT_ZICBOZ		33
 +#define RISCV_ISA_EXT_SVNAPOT		33
++#define RISCV_ISA_EXT_ZICBOZ		34
  
  #define RISCV_ISA_EXT_MAX		64
  #define RISCV_ISA_EXT_NAME_LEN_MAX	32