From: Nicholas Piggin Date: Mon, 15 May 2023 16:19:53 +0000 (+1000) Subject: target/ppc: POWER10 does not have transactional memory X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=4b8732fce9cec7703b49543d612b6e654e0452dd;p=qemu.git target/ppc: POWER10 does not have transactional memory POWER10 hardware implements a degenerate transactional memory facility in POWER8/9 PCR compatibility modes to permit migration from older CPUs, but POWER10 / ISA v3.1 mode does not support it so the CPU model should not support it. Reviewed-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 572cbdf25f..b160926a93 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6573,11 +6573,10 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | + PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_HV) | - (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | (1ull << MSR_EE) | @@ -6617,7 +6616,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; + POWERPC_FLAG_VSX | POWERPC_FLAG_SCV; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; }