From: Frank Li Date: Thu, 14 Dec 2023 19:46:55 +0000 (-0500) Subject: arm64: dts: imx8qm: Correct edma3 power-domains and interrupt numbers X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=5136ea6b109de66b1327a3069f88ad8f5efb37b2;p=linux.git arm64: dts: imx8qm: Correct edma3 power-domains and interrupt numbers It is eDMA1 at QM, which have the same register with eDMA3 at qxp. The below commit fix panic problem. commit b37e75bddc35 ("arm64: dts: imx8qm: Add imx8qm's own pm to avoid panic during startup") This fixes the IRQ and DMA channel numbers. While QM eDMA1 technically has 32 channels, only 10 channels are likely used for I2C. The exact IRQ numbers for the remaining channels were unclear in the reference manual. Fixes: e4d7a330fb7a ("arm64: dts: imx8: add edma[0..3]") Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi index 453fabfd17b81..cafc1383115ab 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -96,7 +96,20 @@ status = "okay"; }; +/* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 */ &edma3 { + reg = <0x5a9f0000 0x210000>; + dma-channels = <10>; + interrupts = , + , + , + , + , + , + , + , + , + ; power-domains = <&pd IMX_SC_R_DMA_1_CH0>, <&pd IMX_SC_R_DMA_1_CH1>, <&pd IMX_SC_R_DMA_1_CH2>, @@ -104,7 +117,9 @@ <&pd IMX_SC_R_DMA_1_CH4>, <&pd IMX_SC_R_DMA_1_CH5>, <&pd IMX_SC_R_DMA_1_CH6>, - <&pd IMX_SC_R_DMA_1_CH7>; + <&pd IMX_SC_R_DMA_1_CH7>, + <&pd IMX_SC_R_DMA_1_CH8>, + <&pd IMX_SC_R_DMA_1_CH9>; }; &flexcan1 {