From: Richard Henderson <rth@twiddle.net>
Date: Mon, 24 Aug 2015 15:01:52 +0000 (-0700)
Subject: target-tilegx: Handle v4int_l/h
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=5151c69abcc049a587b894f0b8e19e1c6d72dc1d;p=qemu.git

target-tilegx: Handle v4int_l/h

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---

diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 7fb2ffb8bb..7719132f89 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1148,10 +1148,18 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
     case OE_RRR(V4ADDSC, 0, X1):
     case OE_RRR(V4ADD, 0, X0):
     case OE_RRR(V4ADD, 0, X1):
+        return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
     case OE_RRR(V4INT_H, 0, X0):
     case OE_RRR(V4INT_H, 0, X1):
+        tcg_gen_shri_tl(tdest, tsrcb, 32);
+        tcg_gen_deposit_tl(tdest, tsrca, tdest, 0, 32);
+        mnemonic = "v4int_h";
+        break;
     case OE_RRR(V4INT_L, 0, X0):
     case OE_RRR(V4INT_L, 0, X1):
+        tcg_gen_deposit_tl(tdest, tsrcb, tsrca, 32, 32);
+        mnemonic = "v4int_l";
+        break;
     case OE_RRR(V4PACKSC, 0, X0):
     case OE_RRR(V4PACKSC, 0, X1):
     case OE_RRR(V4SHLSC, 0, X0):