From: Krzysztof Kozlowski Date: Fri, 26 Jun 2020 08:06:37 +0000 (+0200) Subject: ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=5720fcdc2e5af74e51c5e3102fcefd9fb061a666;p=linux.git ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema Fix dtschema validator warnings like: l2-cache: $nodename:0: 'l2-cache' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 9c207a690df50..f0af1bf2b4d8e 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -71,7 +71,7 @@ interrupt-parent = <&gic>; ranges = <0 0xfc000000 0x2000000>; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0x100000 0x100000>; interrupts = <0 15 4>; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 696e6982a688b..3ee7967c202d5 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -381,7 +381,7 @@ interrupts = <1 13 0xf01>; }; - l2: l2-cache { + l2: cache-controller { compatible = "arm,pl310-cache"; reg = <0x00a10000 0x100000>; interrupts = <0 15 4>;