From: Paloma Arellano Date: Thu, 22 Feb 2024 19:40:02 +0000 (-0800) Subject: drm/msm/dpu: modify timing engine programming for YUV420 over DP X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=57d6ca4c191777d5bb183762f7023ebdc63f45ce;p=linux.git drm/msm/dpu: modify timing engine programming for YUV420 over DP Adjust the encoder timing engine setup programming in the case of video mode for YUV420 over DP to accommodate CDM. Changes in v3: - Move drm_display_mode's hskew division to another patch - Minor cleanup Changes in v2: - Move timing engine programming to this patch Signed-off-by: Paloma Arellano Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/579634/ Link: https://lore.kernel.org/r/20240222194025.25329-18-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov --- diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index e956de1bb2ae6..2ff44295fc9d4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -236,7 +236,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( struct drm_display_mode mode; struct dpu_hw_intf_timing_params timing_params = { 0 }; const struct dpu_format *fmt = NULL; - u32 fmt_fourcc = DRM_FORMAT_RGB888; + u32 fmt_fourcc; unsigned long lock_flags; struct dpu_hw_intf_cfg intf_cfg = { 0 }; @@ -255,7 +255,9 @@ static void dpu_encoder_phys_vid_setup_timing_engine( DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n"); drm_mode_debug_printmodeline(&mode); - if (phys_enc->split_role != ENC_ROLE_SOLO) { + fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc); + + if (phys_enc->split_role != ENC_ROLE_SOLO || fmt_fourcc == DRM_FORMAT_YUV420) { mode.hdisplay >>= 1; mode.htotal >>= 1; mode.hsync_start >>= 1; @@ -275,6 +277,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine( fmt = dpu_get_dpu_format(fmt_fourcc); DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc); + if (phys_enc->hw_cdm) + intf_cfg.cdm = phys_enc->hw_cdm->idx; intf_cfg.intf = phys_enc->hw_intf->idx; intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; intf_cfg.stream_sel = 0; /* Don't care value for video mode */