From: Geert Uytterhoeven Date: Tue, 18 Sep 2018 08:55:29 +0000 (+0200) Subject: clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=5915838b7a4fa6bd6819819de11bfc30a4323ad9;p=linux.git clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment PLL0 runs at 4.8 GHz, i.e. EXTAL x 100. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 7e000d0705891..9eb80180eea0b 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -250,8 +250,8 @@ static const unsigned int r8a77990_crit_mod_clks[] __initconst = { /* * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 *-------------------------------------------------------------------- - * 0 48 x 1 x100/4 x100/3 x100/3 - * 1 48 x 1 x100/4 x100/3 x58/3 + * 0 48 x 1 x100/1 x100/3 x100/3 + * 1 48 x 1 x100/1 x100/3 x58/3 */ #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)