From: Wenbin Mei Date: Wed, 14 Oct 2020 03:08:44 +0000 (+0800) Subject: dt-bindings: mmc: Add support for MT8192 SoC X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=59a23395d8aa2662725ec9f162b9d3b0f34d56ce;p=linux.git dt-bindings: mmc: Add support for MT8192 SoC MT8192 mmc host IP is compatible with MT8183, let's add support for this. Signed-off-by: Wenbin Mei Link: https://lore.kernel.org/r/20201014030846.12428-3-wenbin.mei@mediatek.com Signed-off-by: Ulf Hansson --- diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 79905df75f1df..030e3fdce4929 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -29,26 +29,37 @@ properties: - items: - const: mediatek,mt7623-mmc - const: mediatek,mt2701-mmc + - items: + - const: mediatek,mt8192-mmc + - const: mediatek,mt8183-mmc clocks: description: Should contain phandle for the clock feeding the MMC controller. minItems: 2 - maxItems: 4 + maxItems: 8 items: - description: source clock (required). - description: HCLK which used for host (required). - description: independent source clock gate (required for MT2712). - description: bus clock used for internal register access (required for MT2712 MSDC0/3). + - description: msdc subsys clock gate (required for MT8192). + - description: peripheral bus clock gate (required for MT8192). + - description: AXI bus clock gate (required for MT8192). + - description: AHB bus clock gate (required for MT8192). clock-names: minItems: 2 - maxItems: 4 + maxItems: 8 items: - const: source - const: hclk - const: source_cg - const: bus_clk + - const: sys_cg + - const: pclk_cg + - const: axi_cg + - const: ahb_cg pinctrl-names: items: