From: Clément Léger Date: Wed, 20 Dec 2023 15:57:18 +0000 (+0100) Subject: riscv: hwprobe: export Ztso ISA extension X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=5b4d64a819c05e7e96e7ab3f00f4f0967246905f;p=linux.git riscv: hwprobe: export Ztso ISA extension Export the Ztso extension to userspace. Signed-off-by: Clément Léger Link: https://lore.kernel.org/r/20231220155723.684081-3-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt --- diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 41463b9322689..10bd7b170118e 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -161,6 +161,10 @@ The following keys are defined: defined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified"). + * :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as + defined in the RISC-V ISA manual starting from commit 5618fb5a216b + ("Ztso is now ratified.") + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 91fbe1a7f2e29..01ac3dc196e52 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -56,6 +56,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVFH (1 << 30) #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) +#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index f0bd7b480b7f2..6564fa9e7a7ff 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -174,6 +174,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZKSH); EXT_KEY(ZKT); EXT_KEY(ZIHINTNTL); + EXT_KEY(ZTSO); if (has_vector()) { EXT_KEY(ZVBB);