From: Geert Uytterhoeven Date: Mon, 14 Nov 2022 12:49:02 +0000 (+0100) Subject: arm64: dts: renesas: r8a779g0: Add CPUIdle support X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=5bb355a8d62383b1cbc244897bf6c95724ffbf6e;p=linux.git arm64: dts: renesas: r8a779g0: Add CPUIdle support Support CPUIdle for ARM Cortex-A76 on R-Car V4H. Based on patches in the BSP by Tho Vu and Vincent Bryce. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/f6d4076983eb45cf23595a045747f28cbdcdf4e6.1668429870.git.geert+renesas@glider.be --- diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index dc5f27c114a7a..21baa4936b4fb 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -45,6 +45,7 @@ power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76_0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_1: cpu@100 { @@ -54,6 +55,7 @@ power-domains = <&sysc R8A779G0_PD_A1E0D0C1>; next-level-cache = <&L3_CA76_0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_2: cpu@10000 { @@ -63,6 +65,7 @@ power-domains = <&sysc R8A779G0_PD_A1E0D1C0>; next-level-cache = <&L3_CA76_1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_3: cpu@10100 { @@ -72,8 +75,22 @@ power-domains = <&sysc R8A779G0_PD_A1E0D1C1>; next-level-cache = <&L3_CA76_1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + }; + L3_CA76_0: cache-controller-0 { compatible = "cache"; power-domains = <&sysc R8A779G0_PD_A2E0D0>;