From: Chintan Vankar Date: Mon, 22 Apr 2024 12:45:15 +0000 (+0530) Subject: net: ethernet: ti: am65-cpsw-nuss: Enable SGMII mode for J784S4 CPSW9G X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=5bd8ebe4693c21851ef8a05343d43aa2d005dd53;p=linux.git net: ethernet: ti: am65-cpsw-nuss: Enable SGMII mode for J784S4 CPSW9G TI's J784S4 SoC supports SGMII mode with CPSW9G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the extra_modes member of the "j784s4_cpswxg_pdata" SoC data. Reviewed-by: Roger Quadros Signed-off-by: Chintan Vankar Link: https://lore.kernel.org/r/20240422124515.887511-1-c-vankar@ti.com Signed-off-by: Jakub Kicinski --- diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 81a0fe1f10458..67b3a94e5efa8 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -3390,7 +3390,8 @@ static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { .quirks = 0, .ale_dev_id = "am64-cpswxg", .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_USXGMII), + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | + BIT(PHY_INTERFACE_MODE_USXGMII), }; static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {