From: Bin Meng <bin.meng@windriver.com>
Date: Mon, 8 Jun 2020 14:17:37 +0000 (-0700)
Subject: hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=621c1006d2d82da9f266f21ad8e887c38769a11b;p=qemu.git

hw/riscv: sifive_gpio: Do not blindly trigger output IRQs

At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---

diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index 0d0fd2ba5e..aac6b44cac 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -76,7 +76,9 @@ static void update_state(SIFIVEGPIOState *s)
             actual_value = pull;
         }
 
-        qemu_set_irq(s->output[i], actual_value);
+        if (output_en) {
+            qemu_set_irq(s->output[i], actual_value);
+        }
 
         /* Input value */
         ival = input_en && actual_value;