From: Tony Lindgren Date: Wed, 16 Oct 2019 14:37:06 +0000 (-0700) Subject: ARM: OMAP2+: Allow per oswr for omap4 X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=623429d5b9011cc56538bc70fced765d7c42e622;p=linux.git ARM: OMAP2+: Allow per oswr for omap4 Commit f74297dd9354 ("ARM: OMAP2+: Make sure LOGICRETSTATE bits are not cleared") disabled oswr (open switch retention) for per and core domains as various GPIO related issues were noticed if the bootloader had configured the bits for LOGICRETSTATE for per and core domains. With the recent gpio-omap fixes, mostly related to commit e6818d29ea15 ("gpio: gpio-omap: configure edge detection for level IRQs for idle wakeup"), things now behave for enabling per oswr for omap4. Cc: Merlijn Wajer Cc: Pavel Machek Cc: Sebastian Reichel Signed-off-by: Tony Lindgren --- diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index 63ccd2e028132..d54073d4e46d7 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -136,10 +136,12 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) * we currently will see lost GPIO interrupts for wlcore and * smsc911x at least if per hits retention during idle. */ - if (!strncmp(pwrdm->name, "core", 4) || - !strncmp(pwrdm->name, "l4per", 5)) + if (!strncmp(pwrdm->name, "core", 4) pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_RET); + if (!strncmp(pwrdm->name, "l4per", 5) + pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_OFF); + pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); if (!pwrst) return -ENOMEM;