From: David Jander Date: Fri, 21 Jul 2023 16:53:27 +0000 (+0200) Subject: drm/bridge: tc358767: increase PLL lock time delay X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=63fbe9db8127409d1f2eb7b92034204c21905f1c;p=linux.git drm/bridge: tc358767: increase PLL lock time delay The PLL often fails to lock with this delay. The new value was determined by trial and error increasing the delay bit by bit until the error did not occurr anymore even after several tries. Then double that value was taken as the minimum delay to be safe. Signed-off-by: David Jander Signed-off-by: Lucas Stach Reviewed-by: Marek Vasut Tested-by: Marek Vasut # TC9595 Reviewed-by: Marek Vasut Signed-off-by: Marek Vasut Link: https://patchwork.freedesktop.org/patch/msgid/20230721165328.3968759-1-l.stach@pengutronix.de --- diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index eaa7edb080fa6..40d52f6f073c2 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -500,8 +500,8 @@ static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) if (ret) return ret; - /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ - usleep_range(3000, 6000); + /* Wait for PLL to lock: up to 7.5 ms, depending on refclk */ + usleep_range(15000, 20000); return 0; }