From: Bo-Chen Chen Date: Thu, 10 Nov 2022 06:37:14 +0000 (+0800) Subject: arm64: dts: mt8195: Add edptx and dptx nodes X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=64196979f91832b7b7bae1fb60f7998b7b88935f;p=linux.git arm64: dts: mt8195: Add edptx and dptx nodes In MT8195, we use edptx as the internal display interface and use dptx as the external display interface. Therefore, we need to add these nodes to support the internal display and the external display. - Add dp calibration data in the efuse node. - Add edptx and dptx nodes for MT8195. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221110063716.25677-3-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger --- diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 62a1d06a7f2d5..5d31536f4c486 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1377,6 +1377,9 @@ reg = <0x193 0x1>; bits = <0 4>; }; + dp_calibration: dp-data@1ac { + reg = <0x1ac 0x10>; + }; }; u3phy2: t-phy@11c40000 { @@ -2355,5 +2358,27 @@ clock-names = "engine", "pixel", "pll"; status = "disabled"; }; + + edp_tx: edp-tx@1c500000 { + compatible = "mediatek,mt8195-edp-tx"; + reg = <0 0x1c500000 0 0x8000>; + nvmem-cells = <&dp_calibration>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; + interrupts = ; + max-linkrate-mhz = <8100>; + status = "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible = "mediatek,mt8195-dp-tx"; + reg = <0 0x1c600000 0 0x8000>; + nvmem-cells = <&dp_calibration>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts = ; + max-linkrate-mhz = <8100>; + status = "disabled"; + }; }; };