From: Jernej Skrabec Date: Mon, 3 Dec 2018 19:58:56 +0000 (+0100) Subject: clk: sunxi-ng: h3: Allow parent change for ve clock X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=64f28430cf152e7e2836df37e51c56e31e3647c2;p=linux.git clk: sunxi-ng: h3: Allow parent change for ve clock Cedrus driver wants to set VE clock higher than it's possible without changing parent rate. In order to correct that, allow changing parent rate for VE clock. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 9341ca77c6cd6..e71e2451c2e3d 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -481,7 +481,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0x134, 0, 5, 8, 3, BIT(15), 0); static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", - 0x13c, 16, 3, BIT(31), 0); + 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 0x140, BIT(31), CLK_SET_RATE_PARENT);