From: Jernej Skrabec Date: Sat, 8 Dec 2018 18:02:22 +0000 (+0100) Subject: clk: sunxi-ng: a64: Allow parent change for VE clock X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=67ee606a6bbb5ed2df86e968b6d0d60ad6c60b76;p=linux.git clk: sunxi-ng: a64: Allow parent change for VE clock Cedrus driver wants to set VE clock higher than it's possible without changing parent rate. Allow changing parent rate for VE clock, so clock rate can be set freely. Signed-off-by: Jernej Skrabec Acked-by: Maxime Ripard Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 181b599dc1634..932836d26e2bf 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -570,7 +570,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0x134, 0, 5, 8, 3, BIT(15), 0); static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", - 0x13c, 16, 3, BIT(31), 0); + 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 0x140, BIT(31), CLK_SET_RATE_PARENT);