From: Martin Blumenstingl Date: Tue, 31 Oct 2017 22:23:16 +0000 (+0100) Subject: ARM: dts: meson8: add more L2 cache settings X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=6844e968b54977a1ad55cf8e80c6598369cacff8;p=linux.git ARM: dts: meson8: add more L2 cache settings Amlogic's vendor kernel prints these PL310 L2 cache controller settings during boot: 8 ways, 4096 sets, CACHE_ID 0x4100a0c9, Cache size: 1048576 B AUX_CTRL 0x7ec80001, PERFETCH_CTRL 0x71000007, POWER_CTRL 0x00000000 TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222 Add the "prefetch-data", "prefetch-instr" and "arm,shared-override" properties to get the same L2 cache controller configuration as the vendor kernel. Two differences still remain: - L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0 driver - bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h Signed-off-by: Martin Blumenstingl Tested-by: Kevin Hilman Signed-off-by: Kevin Hilman --- diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 2d7a0752a4608..af3aa7058c5a4 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -308,6 +308,9 @@ arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; arm,filter-ranges = <0x100000 0xc0000000>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; }; &pwm_ab {