From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 8 Mar 2023 18:33:17 +0000 (+0100)
Subject: arm64: dts: qcom: sm8450-hdk: align WCD9385 reset pin with downstream config
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=6b2777fff8a9942cdcee82ae3f17d7f483a1e18c;p=linux.git

arm64: dts: qcom: sm8450-hdk: align WCD9385 reset pin with downstream config

Downstream DTS uses 16 mA drive strength for the WCD9385 audio codec
RESET_N reset pin.  It also pulls the pin down in shutdown mode, thus it
is more like a shutdown pin, not a reset.  Use the same settings here
for HDK8450 and keep the WCD9385 by default in powered off (so pin as
low).  Align the name of pin configuration node with other pins in the
DTS.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308183317.559253-2-krzysztof.kozlowski@linaro.org
---

diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index c97e775e00b3a..e931545a2cac4 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -810,9 +810,11 @@
 		output-low;
 	};
 
-	wcd_default: wcd-default-state {
+	wcd_default: wcd-reset-n-active-state {
 		pins = "gpio43";
 		function = "gpio";
+		drive-strength = <16>;
 		bias-disable;
+		output-low;
 	};
 };