From: Rémi Denis-Courmont Date: Tue, 12 Jan 2021 10:45:08 +0000 (+0200) Subject: target/arm: revector to run-time pick target EL X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=6b340aeb48e4f7f983e1c38790de65ae93079840;p=qemu.git target/arm: revector to run-time pick target EL On ARMv8-A, accesses by 32-bit secure EL1 to monitor registers trap to the upper (64-bit) EL. With Secure EL2 support, we can no longer assume that that is always EL3, so make room for the value to be computed at run-time. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson Message-id: 20210112104511.36576-16-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell --- diff --git a/target/arm/translate.c b/target/arm/translate.c index 528b93dffa..614a6853ca 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1094,6 +1094,22 @@ static void unallocated_encoding(DisasContext *s) default_exception_el(s)); } +static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, + TCGv_i32 tcg_el) +{ + TCGv_i32 tcg_excp; + TCGv_i32 tcg_syn; + + gen_set_condexec(s); + gen_set_pc_im(s, s->pc_curr); + tcg_excp = tcg_const_i32(excp); + tcg_syn = tcg_const_i32(syn); + gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn, tcg_el); + tcg_temp_free_i32(tcg_syn); + tcg_temp_free_i32(tcg_excp); + s->base.is_jmp = DISAS_NORETURN; +} + /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { @@ -2818,8 +2834,11 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, /* If we're in Secure EL1 (which implies that EL3 is AArch64) * then accesses to Mon registers trap to EL3 */ - exc_target = 3; - goto undef; + TCGv_i32 tcg_el = tcg_const_i32(3); + + gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el); + tcg_temp_free_i32(tcg_el); + return false; } break; case ARM_CPU_MODE_HYP: