From: Catalin Marinas Date: Fri, 8 Nov 2019 17:46:11 +0000 (+0000) Subject: Merge branches 'for-next/elf-hwcap-docs', 'for-next/smccc-conduit-cleanup', 'for... X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=6be22809e5c8f286877127e8a24c13c959b9fb4e;p=linux.git Merge branches 'for-next/elf-hwcap-docs', 'for-next/smccc-conduit-cleanup', 'for-next/zone-dma', 'for-next/relax-icc_pmr_el1-sync', 'for-next/double-page-fault', 'for-next/misc', 'for-next/kselftest-arm64-signal' and 'for-next/kaslr-diagnostics' into for-next/core * for-next/elf-hwcap-docs: : Update the arm64 ELF HWCAP documentation docs/arm64: cpu-feature-registers: Rewrite bitfields that don't follow [e, s] docs/arm64: cpu-feature-registers: Documents missing visible fields docs/arm64: elf_hwcaps: Document HWCAP_SB docs/arm64: elf_hwcaps: sort the HWCAP{, 2} documentation by ascending value * for-next/smccc-conduit-cleanup: : SMC calling convention conduit clean-up firmware: arm_sdei: use common SMCCC_CONDUIT_* firmware/psci: use common SMCCC_CONDUIT_* arm: spectre-v2: use arm_smccc_1_1_get_conduit() arm64: errata: use arm_smccc_1_1_get_conduit() arm/arm64: smccc/psci: add arm_smccc_1_1_get_conduit() * for-next/zone-dma: : Reintroduction of ZONE_DMA for Raspberry Pi 4 support arm64: mm: reserve CMA and crashkernel in ZONE_DMA32 dma/direct: turn ARCH_ZONE_DMA_BITS into a variable arm64: Make arm64_dma32_phys_limit static arm64: mm: Fix unused variable warning in zone_sizes_init mm: refresh ZONE_DMA and ZONE_DMA32 comments in 'enum zone_type' arm64: use both ZONE_DMA and ZONE_DMA32 arm64: rename variables used to calculate ZONE_DMA32's size arm64: mm: use arm64_dma_phys_limit instead of calling max_zone_dma_phys() * for-next/relax-icc_pmr_el1-sync: : Relax ICC_PMR_EL1 (GICv3) accesses when ICC_CTLR_EL1.PMHE is clear arm64: Document ICC_CTLR_EL3.PMHE setting requirements arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear * for-next/double-page-fault: : Avoid a double page fault in __copy_from_user_inatomic() if hw does not support auto Access Flag mm: fix double page fault on arm64 if PTE_AF is cleared x86/mm: implement arch_faults_on_old_pte() stub on x86 arm64: mm: implement arch_faults_on_old_pte() on arm64 arm64: cpufeature: introduce helper cpu_has_hw_af() * for-next/misc: : Various fixes and clean-ups arm64: kpti: Add NVIDIA's Carmel core to the KPTI whitelist arm64: mm: Remove MAX_USER_VA_BITS definition arm64: mm: simplify the page end calculation in __create_pgd_mapping() arm64: print additional fault message when executing non-exec memory arm64: psci: Reduce the waiting time for cpu_psci_cpu_kill() arm64: pgtable: Correct typo in comment arm64: docs: cpu-feature-registers: Document ID_AA64PFR1_EL1 arm64: cpufeature: Fix typos in comment arm64/mm: Poison initmem while freeing with free_reserved_area() arm64: use generic free_initrd_mem() arm64: simplify syscall wrapper ifdeffery * for-next/kselftest-arm64-signal: : arm64-specific kselftest support with signal-related test-cases kselftest: arm64: fake_sigreturn_misaligned_sp kselftest: arm64: fake_sigreturn_bad_size kselftest: arm64: fake_sigreturn_duplicated_fpsimd kselftest: arm64: fake_sigreturn_missing_fpsimd kselftest: arm64: fake_sigreturn_bad_size_for_magic0 kselftest: arm64: fake_sigreturn_bad_magic kselftest: arm64: add helper get_current_context kselftest: arm64: extend test_init functionalities kselftest: arm64: mangle_pstate_invalid_mode_el[123][ht] kselftest: arm64: mangle_pstate_invalid_daif_bits kselftest: arm64: mangle_pstate_invalid_compat_toggle and common utils kselftest: arm64: extend toplevel skeleton Makefile * for-next/kaslr-diagnostics: : Provide diagnostics on boot for KASLR arm64: kaslr: Check command line before looking for a seed arm64: kaslr: Announce KASLR status on boot --- 6be22809e5c8f286877127e8a24c13c959b9fb4e diff --cc Documentation/arm64/cpu-feature-registers.rst index 2955287e9acc8,7c40e4581bae5,2955287e9acc8,2955287e9acc8,2955287e9acc8,2955287e9acc8,b86828f86e398,2955287e9acc8,2955287e9acc8..b6e44884e3ada --- a/Documentation/arm64/cpu-feature-registers.rst +++ b/Documentation/arm64/cpu-feature-registers.rst @@@@@@@@@@ -168,8 -168,8 -168,8 -168,8 -168,8 -168,8 -168,15 -168,8 -168,8 +168,15 @@@@@@@@@@ infrastructure +------------------------------+---------+---------+ ------ -- 3) MIDR_EL1 - Main ID Register ++++++ ++ 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 ++++++ ++ +------------------------------+---------+---------+ ++++++ ++ | Name | bits | visible | ++++++ ++ +------------------------------+---------+---------+ ++++++ ++ | SSBS | [7-4] | y | ++++++ ++ +------------------------------+---------+---------+ + + ++++ ++ ++++++ ++ 4) MIDR_EL1 - Main ID Register +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ diff --cc arch/arm64/include/asm/daifflags.h index 9207cd5aa39e2,063c964af705f,063c964af705f,063c964af705f,53cd5fab79a85,063c964af705f,063c964af705f,063c964af705f,063c964af705f..72acd2db167f0 --- a/arch/arm64/include/asm/daifflags.h +++ b/arch/arm64/include/asm/daifflags.h @@@@@@@@@@ -8,8 -8,7 -8,7 -8,7 -8,8 -8,7 -8,7 -8,7 -8,7 +8,9 @@@@@@@@@@ #include #include ++++ ++++#include #include ++++++++#include #define DAIF_PROCCTX 0 #define DAIF_PROCCTX_NOIRQ PSR_I_BIT diff --cc arch/arm64/kernel/cpu_errata.c index e2c4ca1e636ed,f593f4cffc0dd,9c0b011eee20b,f593f4cffc0dd,f593f4cffc0dd,f593f4cffc0dd,f593f4cffc0dd,f593f4cffc0dd,f593f4cffc0dd..4f8187a4fc466 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@@@@@@@@@ -632,45 -623,9 -610,9 -623,9 -623,9 -623,9 -623,9 -623,9 -623,9 +619,45 @@@@@@@@@@ check_branch_predictor(const struct arm return (need_wa > 0); } --------#ifdef CONFIG_HARDEN_EL2_VECTORS ++++++++static const __maybe_unused struct midr_range tx2_family_cpus[] = { ++++++++ MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), ++++++++ MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), ++++++++ {}, ++++++++}; ++++++++ ++++++++static bool __maybe_unused ++++++++needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, ++++++++ int scope) ++++++++{ ++++++++ int i; ++++++++ ++++++++ if (!is_affected_midr_range_list(entry, scope) || ++++++++ !is_hyp_mode_available()) ++++++++ return false; ++++++++ ++++++++ for_each_possible_cpu(i) { ++++++++ if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0) ++++++++ return true; ++++++++ } ++++++++ ++++++++ return false; ++++++++} ++++++++ ++++++++static bool __maybe_unused ++++++++has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, ++++++++ int scope) ++++++++{ ++++++++ u32 midr = read_cpuid_id(); ++++++++ bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT); ++++++++ const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); + - ------static const struct midr_range arm64_harden_el2_vectors[] = { ++++++++ WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); ++++++++ return is_midr_in_range(midr, &range) && has_dic; ++++++++} ++++++++ ++++++++#if defined(CONFIG_HARDEN_EL2_VECTORS) || defined(CONFIG_ARM64_ERRATUM_1319367) + ++++++ - static const struct midr_range arm64_harden_el2_vectors[] = { ++++++++static const struct midr_range ca57_a72[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), {},